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silego technology, inc. rev 1.05 SLG46536_ds_105 revised october 12, 2017 greenpak programmable mixed-signal matrix SLG46536 block diagram features ? logic & mixed signal circuits ? highly versatile macrocells ? read back protection (read lock) ? 1.8 v (5%) to 5 v (10%) supply ? operating temperature range: -40c to 85c ? rohs compliant / halogen-free ? 14-pin stqfn: 2 x 2.2 x 0.55 mm, 0.4 mm pitch applications ? personal computers and servers ? pc peripherals ? consumer electronics ? data communications equipment ? handheld and portable electronics pin configuration gnd gpio gpio gpio gpio 2 3 49 10 11 gpi vdd 1 14-pin stqfn (top view) gpio scl/gpio 8 67 14 13 sda/gpio gpio gpio gpio gpio 5 12 acmp0 acmp1 acmp2 3-bit lut3_4 or dff7 programmable delay additional logic functions combination function macrocells 2-bit lut2_0 or dff0 2-bit lut2_2 or dff2 2-bit lut2_1 or dff1 3bit lut3_0 or dff3 3-bit lut3_2 or dff5 3-bit lut3_1 or dff4 3-bit lut3_12 or dff9 3-bit lut3_11 or dff8 filter_1 with edge detect por i 2 c serial communication 3-bit lut3_5 or cnt/dly2 3-bit lut3_6 or cnt/dly3 3-bit lut3_7 or cnt/dly4 3-bit lut3_8 or cnt/dly5 3-bit lut3_9 or cnt/dly6 3-bit lut3_10 or pipe delay fiter_0 with edge detect 16x8 ram memory with defined nvm otp initial state 4-bit lut lut4_2 3-bit lut3_14 or dff11 3-bit lut3_16 or dff13 3-bit lut3_15 or dff12 2-bit lut2_3 or pgen 3-bit lut3_3 or dff6 3-bit lut3_13 or dff10 3-bit lut3_17 or dff14 4-bit lut4_0 or cnt/dly0 4-bit lut4_1 or cnt/dly1 vref crystal oscillator pin 4 gpio pin 5 gpio pin 1 vdd pin 2 gpi pin 3 gpio pin 14 gpio pin 6 scl or gpio pin 7 sda or gpio pin 8 gpio pin 12 gpio pin 11 gpio pin 10 gpio pin 9 gnd pin 13 gpio rc oscillator 25m oscillator
SLG46536_ds_105 page 1 of 164 SLG46536 1.0 overview the SLG46536 provides a small, low power component for commonly used mixed-signal functions. the user creates their circuit design by programming the one time non-volatile memory (nvm) to configure the interconnect logic, the i/o pins and the macrocells of the SLG46536. this highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single in tegrated circuit. the macrocells in the device include the following: ? three analog comparators (acmp) ? twenty-six combination function macrocells ? three selectable dff/latch or 2-bit luts ? one selectable continuous dff/latch or 3-bit lut ? eleven selectable dff/latch or 3-bit luts ? one selectable pipe delay or 3-bit lut ? one selectable programmable pattern generator or 2-bit lut ? five 8-bit delays/co unters or 3-bit luts ? two 16-bit delays/co unters or 4-bit luts ? two deglitch filters with edge detectors ? combinatorial logic ? one 4-bit lut ? serial communications ?i 2 c protocol compliant ? 16x8 ram memory w ith defined nvm otp initial state ? pipe delay C 16 sta ge/3 output (part of c ombination function m acrocell) ? programmable delay ? two oscillators (osc) ? configurable 25 khz/2 mhz ? 25 mhz rc oscillator ? crystal oscillator ? power-on-reset (por)
SLG46536_ds_105 page 2 of 164 SLG46536 2.0 pin description 2.1 functional pin description pin # pin name function 1 vdd power supply 2 gpi general purpose input 3 gpio general purpose i/o 4 gpio general purpose i/o or acmp0 (+) 5 gpio general purpose i/o with oe or external vref (acmp0 in-) 6 scl/gpio general purpose i/o scl or gpiod (nmos open drain only ) 7 sda/gpio general purpose i/o sda or gpiod (nmos open drain only ) 8 gpio general purpose i/ o with oe or acmp1 (+) 9 gnd ground 10 gpio general purpose i/o external vref (acmp1 in-) 11 gpio general pu rpose i/o with oe 12 gpio general pu rpose i/o with oe 13 gpio general purpose i/o 14 gpio general purpose i/o or external clock input
SLG46536_ds_105 page 3 of 164 SLG46536 3.0 user programmability non-volatile memory (nvm) is used to configure the SLG46536s c onnection matrix routing and macrocells. the nvm is one-time-programmable (otp). how ever, silegos greenpak develop ment tools can be used to configure the connection matrix and macrocells, without programming the nvm, to allow on-chip e mulation. this configuration will remain active on the device a s long as it remains powered and c an be re-written as needed to f acilitate rapid design changes. when a design is ready for in-circuit testing, the same greenpa k development tools can be used to program the nvm and create samples for small quantity builds. once the nvm is programmed, the device will retain this conf iguration for the duration of i ts lifetime. once the design is finalized, the design file c an be forwarded to silego to integ rate into the produ ction process. figure 1. steps to create a cu stom silego greenpak device product definition customer creates their own design in greenpak designer program engineering samples with greenpak development tools customer verifies greenpak in system design e-mail design file to greenpak@silego.com e-mail product idea, definition, drawing, or schematic to greenpak@silego.com silego applications engineers will review design specifications with customer samples and design & characterization report sent to customer customer verifies greenpak design custom greenpak part enters production greenpak design approved in system test greenpak design approved greenpak design approved emulate design to verify behavior
SLG46536_ds_105 page 4 of 164 SLG46536 4.0 ordering information part number type SLG46536v 14-pin stqfn SLG46536vtr 14-pin stqfn - tape and reel (3k units)
SLG46536_ds_105 page 5 of 164 SLG46536 5.0 electrical specifications 5.1 absolute maximum conditions 5.2 electrical charac teristics (1.8 v 5% v dd ) parameter min. max. unit supply voltage on vdd relative to gnd -0.5 7 v dc input voltage gnd - 0.5 vdd + 0.5 v maximum average or dc current (through pin) push-pull 1x -- 11 ma push-pull 2x -- 16 od 1x -- 11 od 2x -- 21 od 4x -- 43 current at input pin -1.0 1.0 ma storage temperature range -65 150 c junction temperature -- 150 c esd protection (human body model) 2000 -- v esd protection (charged device model) 1300 -- v moisture sensitivity level 1 symbol parameter condition/note min. typ. max. unit v dd supply voltage 1.71 1.80 1.89 v t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v acmp acmp input voltage range positive input 0 -- v dd v negative input 0 -- 1.2 v v ih high-level input voltage logic input 1.06 -- v dd v logic input with schm itt trigger 1.28 -- v dd v low-level logic input 0.94 -- v dd v v il low-level input voltage logic input 0 -- 0.76 v logic input with schm itt trigger 0 -- 0.49 v low-level logic input 0 -- 0.52 v v hys schmitt trigger hysteresis voltage logic input with schmit t trigger 0.10 0.41 0.66 v i lkg input leakage (absolute value) -- 1 1000 na v oh high-level output voltage push-pull, i oh = 100 ? a, 1x drive 1.69 1.79 -- v pmos od, i oh = 100 ? a, 1x drive 1.69 1.79 -- v push-pull, i oh = 100 ? a, 2x drive 1.70 1.79 -- v pmos od, i oh = 100 ? a, 2x drive 1.70 1.79 -- v
SLG46536_ds_105 page 6 of 164 SLG46536 v ol low-level output voltage push-pull, i ol = 100 ? a, 1x drive -- 0.009 0.013 v push-pull, i ol = 100 ? a, 2x drive -- 0.004 0.006 v open drain, i ol = 100 ? a, 1x drive -- 0.006 0.009 v open drain, i ol = 100 ? a, 2x drive -- 0.003 0.004 v open drain nmos 4x, i ol = 100 ? a -- 0.001 0.002 v i oh high-level output pulse current (see note 1) push-pull, v oh = v dd - 0.2, 1x drive 1.07 1.70 -- ma pmos od, v oh = v dd - 0.2, 1x drive 1.07 1.70 -- ma push-pull, v oh = v dd - 0.2, 2x drive 2.22 3.41 -- ma pmos od, v oh = v dd - 0.2, 2x drive 2.22 3.41 -- ma i ol low-level output pulse current (see note 1) push-pull, v ol = 0.15 v, 1x drive 0.92 1.69 -- ma push-pull, v ol = 0.15 v, 2x drive 1.83 3.38 -- ma open drain, v ol = 0.15 v, 1x drive 1.38 2.53 -- ma open drain, v ol = 0.15 v, 2x drive 2.75 5.07 -- ma open drain nmos 4x, v ol = 0.15 v 7.21 9.00 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 45 ma t j = 110c -- -- 22 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 86 ma t j = 110c -- -- 41 ma v o maximal voltage applied to any pin in high-impedance state -- -- v dd v t su startup time from vdd rising past pon thr 0.63 1.36 1.87 ms pon thr power on threshold v dd level required to start up the chip 1.41 1.54 1.66 v poff thr power off threshold v dd level required to switch off the chip 1.00 1.15 1.31 v r pup pull up resistance 1 m pull up 859.8 1097.1 1358.9 k ? 100 k pull up 86.47 110.13 136.18 k ? 10 k pull up 10.82 12.86 15.36 k ? r pdwn pull down resistance 1 m pull down 873.9 1097.0 1359.0 k ? 100 k pull down 88.89 110.53 136.55 k ? 10 k pull down 9.65 12.75 15.76 k ? note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11 , 12, 13 and 14 to another. symbol parameter condition/note min. typ. max. unit
SLG46536_ds_105 page 7 of 164 SLG46536 5.3 electrical charac teristics (3.3 v 10% v dd ) symbol parameter condition/note min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v t a operating temperature -40 25 85 c v pp programming voltage 7.25 7.50 7.75 v v acmp acmp input voltage range positive input 0 -- v dd v negative input 0 -- 1.2 v v ih high-level input voltage logic input 1.81 -- v dd v logic input with schm itt trigger 2.14 -- v dd v low-level logic input 1.06 -- v dd v v il low-level input voltage logic input 0 -- 1.31 v logic input with schm itt trigger 0 -- 0.97 v low-level logic input 0 -- 0.67 v v hys schmitt trigger hysteresis voltage logic input with schmit t trigger 0.29 0.62 0.94 v i lgk input leakage (absolute value) -- 1 1000 na v oh high-level output voltage push-pull, i oh = 3 ma, 1x drive 2.70 3.12 -- v pmos od, i oh = 3 ma, 1x drive 2.70 3.12 -- v push-pull, i oh = 3 ma, 2x drive 2.85 3.21 -- v pmos od, i oh = 3 ma, 2x drive 2.86 3.21 -- v v ol low-level output voltage push-pull, i ol = 3 ma, 1x drive -- 0.13 0.23 v push-pull, i ol = 3 ma, 2x drive -- 0.06 0.11 v open drain, i ol = 3 ma, 1x drive -- 0.08 0.15 v open drain, i ol = 3 ma, 2x drive -- 0.04 0.08 v open drain nmos 4x, i ol = 3 ? ma -- 0.02 0.04 v i oh high-level output pulse current (see note 1) push-pull, v oh = 2.4 v, 1x drive 6.05 12.08 -- ma pmos od, v oh = 2.4 v, 1x drive 6.05 12.08 -- ma push-pull, v oh = 2.4 v, 2x drive 11.54 24.16 -- ma pmos od, v oh = 2.4 v, 2x drive 11.52 24.16 -- ma i ol low-level output pulse current (see note 1) push-pull, v ol = 0.4 v, 1x drive 4.88 8.24 -- ma push-pull, v ol = 0.4 v, 2x drive 9.75 16.49 -- ma open drain, v ol = 0.4 v, 1x drive 7.31 12.37 -- ma open drain, v ol = 0.4 v, 2x drive 14.54 24.74 -- ma open drain nmos 4x, v ol = 0.4 v 31.32 41.06 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 45 ma t j = 110c -- -- 22 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 86 ma t j = 110c -- -- 41 ma
SLG46536_ds_105 page 8 of 164 SLG46536 v o maximal voltage applied to any pin in high-impedance state -- -- v dd v t su startup time from vdd rising past pon thr 0.61 1.24 1.65 ms pon thr power on threshold v dd level required to start up the chip 1.41 1.54 1.66 v poff thr power off threshold v dd level required to switch off the chip 1.00 1.15 1.31 v r pup pull up resistance 1 m pull up 873.2 1094.7 1364.3 k ? 100 k pull up 85.17 109.30 135.52 k ? 10 k pull up 9.61 11.86 14.73 k ? r pdwn pull down resistance 1 m pull down 862.5 1096.3 1357.4 k ? 100 k pull down 87.95 109.76 136.06 k ? 10 k pull down 8.66 11.81 15.05 k ? note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11 , 12, 13 and 14 to another. symbol parameter condition/note min. typ. max. unit
SLG46536_ds_105 page 9 of 164 SLG46536 5.4 electrical charac teristics (5 v 10% v dd ) symbol parameter condition/note min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v t a operating temperature -40 25 85 c v pp programming volt age 7.25 7.50 7.75 v v acmp acmp input voltage range positive input 0 -- v dd v negative input 0 -- 1.2 v v ih high-level i nput voltage logic input 2.68 -- v dd v logic input with schmitt trigger 3.34 -- v dd v low-level logic input 1.15 -- v dd v v il low-level input voltage logic input 0 -- 1.96 v logic input with schmitt trigger 0 -- 1.41 v low-level logic input 0 -- 0.77 v v hys schmitt trigger hysteresis voltage logic input with schmitt trigger 0.44 0.90 1.38 v i lgk input leakage (absolute value) -- 1 1000 na v oh high-level output voltage push-pull, i oh = 5 ma, 1x drive 4.15 4.76 -- v pmos od, i oh = 5 ma, 1x drive 4.16 4.76 -- v push-pull, i oh = 5 ma, 2x drive 4.32 4.89 -- v pmos od, i oh = 5 ma, 2x drive 4.33 4.89 -- v v ol low-level output voltage push-pull, i ol = 5 ma, 1x drive -- 0.19 0.24 v push-pull, i ol =5 ma, 2x drive -- 0.09 0.12 v open drain, i ol = 5 ma, 1x drive -- 0.12 0.16 v open drain, i ol = 5 ma, 2x drive -- 0.07 0.08 v open drain nmos 4x, i ol = 5 ma -- 0.03 0.05 v i oh high-level output pulse current (see note 1) push-pull, v oh = 2.4 v, 1x drive 22.08 34.04 -- ma pmos od, v oh = 2.4 v, 1x drive 22.08 34.04 -- ma push-pull, v oh = 2.4 v, 2x drive 41.76 68.08 -- ma pmos od, v oh = 2.4 v, 2x drive 41.69 68.08 -- ma i ol low-level output pulse current (see note 1) push-pull, v ol = 0.4 v, 1x drive 7.22 11.58 -- ma push-pull, v ol = 0.4 v, 2x drive 13.83 23.16 -- ma open drain, v ol = 0.4 v, 1x drive 10.82 17.38 -- ma open drain, v ol = 0.4 v, 2x drive 17.34 34.76 -- ma open drain nmos 4x, v ol = 0.4 v 41.06 55.18 -- ma i vdd maximum average or dc current through vdd pin (per chip side, see note 2) t j = 85c -- -- 45 ma t j = 110c -- -- 22 ma i gnd maximum average or dc current through gnd pin (per chip side, see note 2) t j = 85c -- -- 86 ma t j = 110c -- -- 41 ma
SLG46536_ds_105 page 10 of 164 SLG46536 . 5.5 i 2 c specifications v o maximal voltage applied to any pin in high-impedance state -- -- v dd v t su startup time from v dd rising past pon thr 0.60 1.23 1.61 ms pon thr power on threshold v dd level required to start up the chip 1.41 1.54 1.66 v poff thr power off threshold v dd level required to switch off the chip 1.00 1.15 1.31 v r pup pull up resistance 1 m pull up 864.6 1093.4 1348.1 k ? 100 k pull up 84.32 108.97 135.24 k ? 10 k pull up 8.74 11.37 14.52 k ? r pdwn pull down resistance 1 m pull down 873.3 1096.1 1370.5 k ? 100 k pull down 87.57 109.48 135.89 k ? 10 k pull down 7.95 11.33 14.78 k ? note 1: dc or average current through any pin should not exceed value given in absolute maximum conditions. note 2: the greenpak?s power rails are divided in two sides. pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11 , 12, 13 and 14 to another. symbol parameter condition/note min. typ. max. unit f scl clock frequency, scl v dd = (1.71...5.5) v -- -- 400 khz t low clock pulse width low v dd = (1.71...5.5) v 1300 ns t high clock pulse width high v dd = (1.71...5.5) v 600 -- -- ns t i input filter spike suppression (scl, sda) v dd = 1.8 v 5 % -- -- 95 ns v dd = 3.3 v 10% 95 v dd = 5.0 v 10 % 111 t aa clock low to data out valid v dd = (1.71...5.5) v -- -- 900 ns t buf bus free time between stop and start v dd = (1.71...5.5) v 1300 -- -- ns t hd_sta start hold time v dd = (1.71...5.5) v 600 -- -- ns t su_sta start set-up time v dd = (1.71...5.5) v 600 -- -- ns t hd_dat data hold time v dd = (1.71...5.5) v 0 -- -- ns t su_dat data set-up time v dd = (1.71...5.5) v 100 -- -- ns t r inputs rise time v dd = (1.71...5.5) v -- -- 300 ns t f inputs fall time v dd = (1.71...5.5) v -- -- 300 ns t su_sto stop set-up time v dd = (1.71...5.5) v 600 -- -- ns t dh data out hold time v dd = (1.71...5.5) v 50 -- -- ns symbol parameter condition/note min. typ. max. unit
SLG46536_ds_105 page 11 of 164 SLG46536 5.6 idd estimator table 1. typical current estimated for each macrocell at t=25c symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit i current chip quiescent 0.45 0.75 1.12 ? a osc 2 mhz, predivide = 1 41.48 64.00 94.89 ? a osc 2 mhz, predivide = 8 25.68 32.41 43.22 ? a osc 25 khz, predivide = 1 7.16 7.94 9.25 ? a osc 25 khz, predivide = 8 6.97 7.60 8.68 ? a osc 25 mhz, predivide = 1 87.25 238.27 428.66 ? a osc 25 mhz, predivide = 8 78.01 212.45 390.17 ? a acmp (each) 54.96 52.64 60.81 ? a acmp with buffer (each) 75.06 72.74 81.25 ? a vref (each) 49.70 47.32 55.60 ? a vref with buffer (each) 71.93 71.27 79.62 ? a
SLG46536_ds_105 page 12 of 164 SLG46536 5.7 timing estimator 5.8 typical counter/de lay offset measurements table 2. typical delay estimate d for each macrocell at t=25c symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit rising falling rising falling rising falling tpd delay digital input to pp 1x 45 50 19 21 14 15 ns tpd delay digital input with schmitt trigger to pp 1x 44 49 19 21 14 15 ns tpd delay low voltage digital input to pp 1x 46 447 19 195 14 134 ns tpd delay digital input to pmos output 44 - 19 - 14 - ns tpd delay digital input to nmos output - 81 - 30 - 20 ns tpd delay output enable from pin, oe hi-z to 1 48 - 20 - 15 - ns tpd delay output enable from pin, oe hi-z to 0 - 46 - 20 - 24 ns tpd delay lut2bit (latch) 34 33 14 13 10 9 ns tpd delay latch (lut2bit) 30 34 14 13 10 9 ns tpd delaylut3bit (latch) 383718151310ns tpd delay latch+nreset (lut3bit) 45 42 21 17 15 12 ns tpd delay latch 33 5 14 14 ns tpd delay lut4bit 28 33 14 13 10 9 ns tpd delay lut2bit 31 31 14 13 10 9 ns tpd delay lut3bit 35 33 15 13 11 10 ns tpd delaycnt/dly logic 626827291920ns tpd delaydff 3228141211 9 ns tpd delayp_dly1c 626827291920ns tpd delay p_dly2c 667 656 303 297 225 221 ns tpd delay p_dly3c 968 956 440 434 327 322 ns tpd delay p_dly4c 1265 1252 576 570 428 423 ns tpd delay filter 213 210 84 83 55 55 ns tpd delay acmp (5 mv overdrive, in- = 600 mv) 1600 1900 1500 1800 1600 1800 ns tw width i/o with 1x push pull (min transmitted) 20 20 20 20 20 20 ns tw width filter (min transmitted) 150 150 55 55 35 35 ns table 3. typical counter/de lay offset measurements parameter rc osc freq rc osc power v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit offset (power on delay) 25 khz auto 1.6 1.6 1.6 ? s offset (power on delay), fast start 25 khz auto 2.1 2.1 2.1 ? s offset (power on delay) 2 mhz auto 0.4 0.2 0.2 ? s offset (power on delay), fast start 2 mhz auto 0.7 0.5 0.4 ? s offset (power on delay) 2 5 mhz auto 0.01 0.05 0.04 ? s frequency settling time 25 khz auto 19 14 12 ? s frequency settling time 2 mhz auto 14 14 14 ? s variable (clk period) 25 khz forced 0-40 0-40 0-40 ? s variable (clk period) 2 mhz forced 0-0.5 0-0.5 0-0.5 ? s variable (clk period) 25 mhz 0-0.04 0-0.04 0-0.04 ? s
SLG46536_ds_105 page 13 of 164 SLG46536 5.9 expected delays and widths 5.10 typical pulse width performance tpd (non-delayed edge) 25 khz/ 2 mhz either 35 14 10 ns table 4. expected delays and widths (typical) symbol parameter note v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit width width, 1 cell mode:(any)edge detect, edge detect output 296 1 35 101 ns width width, 2 cell mode:(any)edge detect, edge detect output 597 2 72 203 ns width width, 3 cell mode:(any)edge detect, edge detect output 898 4 10 305 ns width width, 4 cell mode:(any)edge detect, edge detect output 1195 546 407 ns time1 delay, 1 cell mode:(any)edge detect, edge detect output 55 24 18 ns time1 delay, 2 cell mode:(any)edge detect, edge detect output 55 24 18 ns time1 delay, 3 cell mode:(any)edge detect, edge detect output 55 24 18 ns time1 delay, 4 cell mode:(any)edge detect, edge detect output 55 24 18 ns time2 delay, 1 cell m ode: both edge delay, edg e detect output 367 165 106 ns time2 delay, 2 cell m ode: both edge delay, edg e detect output 667 300 193 ns time2 delay, 3 cell m ode: both edge delay, edg e detect output 968 440 279 ns time2 delay, 4 cell m ode: both edge delay, edg e detect output 126 5 575 365 ns table 5. typical pulse widt h performance at t=25c parameter v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit filtered pulse width for filter 0 < 114 < 47 < 30 ns filtered pulse width for filter 1 <75 <30 <19 ns table 3. typical counter/de lay offset measurements parameter rc osc freq rc osc power v dd = 1.8 v v dd = 3.3v v dd = 5.0v unit
SLG46536_ds_105 page 14 of 164 SLG46536 5.11 osc specifications table 6. 25 khz rc osc0 frequency limits power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c minimum value, khz maximum value, khz minimum value, khz maximum value, khz minimum value, khz maximum value, khz 1.8 v 5% 24.240 25.781 21.963 27.188 21.963 27.562 3.3 v 10% 24.447 25.556 21.905 27.221 21.905 27.263 5 v 10% 24.315 25.911 22.045 27.099 22.045 27.422 2.5 v ... 4.5 v 24.398 25.576 21.897 27.221 21.897 27.277 1.71 v 5.5 v 24.089 26.1 28 21.897 27.373 21.897 27.613 table 7. 25 khz rc osc0 frequen cy error (error cal culated relati ve to nominal value) power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) 1.8 v 5% -2.76% 3.42% -1 1.89% 9.07% -11.89% 10.57% 3.3 v 10% -2.01% 2.43% - 12.20% 9.11% -12.20% 9.28% 5 v 10% -2.51% 3.89% -11. 61% 8.65% -11.61% 9.95% 2.5 v ... 4.5 v -2.21% 2.52% -12.23% 9.11% -12.23% 9.33% 1.71 v 5.5 v -3.44% 4.73% -12.23% 9.72% -12.23% 10.68%
SLG46536_ds_105 page 15 of 164 SLG46536 5.11.1 2 mhz rc oscillator table 8. 2 mhz rc osc0 frequency limits power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c minimum value, mhz maximum value, mhz minimum value, mhz maximum value, mhz minimum value, mhz maximum value, mhz 1.8 v 5% 1.932 2.058 1.793 2.171 1.793 2.171 3.3 v 10% 1.932 2.099 1. 808 2.204 1.808 2.204 5 v 10% 1.981 2.194 1.759 2.316 1.759 2.316 2.5 v ... 4.5 v 1.920 2.120 1.800 2.214 1.800 2.214 1.71 v 5.5 v 1.811 2.288 1.710 2.337 1.710 2.361 table 9. 2 mhz rc osc0 f requency error (error calculated relativ e to nominal value) power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) 1.8 v 5% -3.23% 3.10% -10. 21% 8.73% -10.21% 8.73% 3.3 v 10% -3.40% 4.94% -9 .60% 10.19% -9.60% 10.19% 5 v 10% -5.44% 9.70% - 12.03% 2.32% -12.03% 15.81% 2.5 v ... 4.5 v -4.00% 5.98% -9.99% 10.68% -9.99% 10.68% 1.71 v 5.5 v -9.46% 14.4 2% -14.48% 16.85% -14.48% 18.05%
SLG46536_ds_105 page 16 of 164 SLG46536 5.11.2 25 mhz rc oscillator note 1: operating 25 mhz rc osc1 is not recommended at vdd < 2.5 v. table 10. 25 mhz rc os c1 frequency limits power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c minimum value, mhz maximum value, mhz minimum value, mhz maximum value, mhz minimum value, mhz maximum value, mhz 2.5 v 10% 22.344 27.023 21.687 27.777 21.687 27.706 3.3 v 10% 22.412 26.290 21.399 26.595 21.399 27.069 5 v 10% 23.049 26.646 21.900 27.220 21.900 27.647 2.5 v ... 4.5 v 21.511 26.29 0 20.738 26.685 20.738 27.123 1.71 v 5.5 v (see note1) 13.290 26.290 12.770 26.685 11.908 27.123 table 11. 25 mhz rc osc1 frequency error (error calculated relat ive to nominal value) power supply range (vdd) v temperature range +25 c 0 c ... +85 c -40 c ... +85 c error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) error (% at minimum) error (% at maximum) 2.5 v 10% -10.37% 8.40% - 13.00% 9.42% -13.00% 11.14% 3.3 v 10% -11.10% 4.28% - 15.12% 5.49% -15.12% 7.37% 5 v 10% -9.80% 4.27% -14. 30% 6.52% -14.30% 8.19% 2.5 v ... 4.5 v -14.68% 4.28% -17.74% 5.85% -17.74% 7.58% 1.71 v 5.5 v (see note1) -47.29 % 4.28% -49.35% 5.85% -52.77% 7.58%
SLG46536_ds_105 page 17 of 164 SLG46536 5.11.3 osc power on delay table 12. oscillators power on delay at room temperature, dly/cn t counter data = 100; rc osc power setting: "auto power on", rc osc clock to matrix input: "enable" power supply range (vdd) v rc osc0 2 mhz rc osc0 25 khz rc osc1 typical value, s maximum value, s typical value, ms maximum value, ms typical value, s maximum value, s 1.71 368.7 402.3 16.26 17.87 114.4 134.8 1.80 347.0 375.4 15.93 17.79 104.9 122.0 1.89 329.4 354.2 15.58 17.67 96.5 111.5 2.50 278.4 295.2 14.08 16.75 72.0 80.3 2.70 263.2 277.8 13.20 16.21 65.0 71.4 3.00 251.6 264.9 8.38 9.11 60.0 65.1 3.30 238.3 250.6 1.64 2.02 55.2 58.7 3.60 228.3 240.0 1.57 1.92 51.7 55.0 4.20 220.3 231.7 1.55 1.93 49.1 51.9 4.50 208.0 219.2 1.55 2.01 45.5 47.8 5.00 203.0 213.9 1.56 2.01 44.3 46.5 5.50 195.7 206.5 1.58 2.07 43.0 44.8 table 13. oscillators power on delay at room temperature, dly/cn t counter data = 100; rc osc power setting: "auto power on", rc osc clock to matrix input: "enable", fast start-u p time mode power supply range (vdd) v rc osc0 2 mhz rc osc0 25 khz typical value, s maximum value, s typical value, ms maximum value, ms 1.71 741.8 924.7 20.78 21.36 1.80 703.9 861.5 20.80 21.26 1.89 672.5 809.0 20.81 21.42 2.50 578.5 651.8 20.84 21.40 2.70 546.8 592.8 20.88 21.42 3.00 520.6 549.2 20.93 21.63 3.30 490.4 515.8 21.00 21.65 3.60 468.9 504.7 21.09 21.75 4.20 453.0 496.6 21.18 21.98 4.50 430.1 478.2 21.36 22.34 5.00 420.7 468.5 21.39 22.34 5.50 406.1 451.9 21.38 22.34
SLG46536_ds_105 page 18 of 164 SLG46536 5.12 acmp specifications table 14. acmp specifications symbol parameter description/note conditions min. typ. max. unit v acmp acmp input voltage range positive input vdd = 1.8 v 5 % 0--v dd v negative input 0 -- 1.2 v positive input vdd = 3.3 v 10 % 0--v dd v negative input 0 -- 1.2 v positive input vdd = 5.0 v 10 % 0--v dd v negative input 0 -- 1.2 v v offset acmp input offset voltage low bandwidth - enable, vhys = 0 mv, gain = 1, vref = (50..1200) mv, vdd = (1.71..5.5) v t = 25c -9.1 -- 8.4 mv t = (-40..85)c -10.9 -- 10.9 mv low bandwidth - disable, vhys = 0 mv, gain =1, vref = (50..1200) mv, vdd = (1.71..5.5) v t = 25c -7.5 -- 7.2 mv t = (-40..85)c -10.7 -- 10.5 mv t start acmp start time acmp power on delay, minimal required wake time for the "wake and sleep function", regulator and charge pump set to automatic on/off bg = 550 s, t = 25c vdd = (1.71..5.5) v -- 609.7 862.2 s bg = 550 s, t = (-40..85)c vdd = (1.71..5.5) v -- 675.0 1028.8 s bg = 100 s, t = 25c vdd = 2.7..5.5 v -- 132.4 176.2 s bg = 100 s, t = (-40..85)c vdd = 2.7..5.5 v -- 149.4 213.5 s acmp power on delay, minimal required wake time for the "wake and sleep function", regulator and charge pump always off bg = 550 s, t = 25c vdd = (3..5.5) v -- 609.5 862.0 s bg = 550 s, t = (-40..85)c vdd = (3..5.5) v -- 674.6 1027.5 s bg = 100 s, t = 25c vdd = 3..5.5 v -- 131.6 176.0 s bg = 100 s, t = (-40..85)c vdd = 3..5.5 v -- 149.2 213.3 s
SLG46536_ds_105 page 19 of 164 SLG46536 v hys built-in hysteresis v hys = 25 mv v il = vin - v hys /2 v ih = vin + v hys /2 lb - enabled, t = 25c 7.32 -- 35.5 mv lb - disabled, t = 25c 10.0 -- 38.5 mv v hys = 50 mv v il = vin - v hys v ih = v hys lb - enabled, t = 25c 42.9 -- 57.8 mv lb - disabled, t = 25c 44.2 -- 54.3 mv v hys = 200 mv v il = vin - v hys v ih = v hys lb - enabled, t = 25c 192.7 -- 208.7 mv lb - disabled, t = 25c 193.3 -- 204.8 mv v hys = 25 mv v il = vin - v hys /2 v ih = vin + v hys /2 lb - enabled, t = (-40+85)c 0.0 -- 58.0 mv lb - disabled, t = (-40+85)c 0.0 -- 52.9 mv v hys = 50 mv v il = vin - v hys v ih = v hys lb - enabled, t = (-40+85)c 22.5 -- 86.9 mv lb - disabled, t = (-40+85)c 29.2 -- 76.5 mv v hys = 200 mv v il = vin - v hys v ih = v hys lb - enabled, t = (-40+85)c 157.1 -- 251.6 mv lb - disabled, t = (-40+85)c 160.2 -- 245.3 mv r sin series input resistance gain = 1x -- 100.0 -- ?? gain = 0.5x -- 1.0 -- ?? gain = 0.33x -- 0.8 -- ?? gain = 0.25x -- 1.0 -- ?? prop propagation delay, response time low bandwidth - enable, gain = 1, vdd=(1.71..3.3)v, overdrive=5 mv low to high, t = (-40+85)c -- 103.93 1853.68 s high to low, t = (-40+85)c -- 101.06 1656.70 s low bandwidth - disable, gain = 1, vdd=(1.71..3.3)v, overdrive=5 mv low to high, t = (-40+85)c -- 68.29 1753.33 s high to low, t = (-40+85)c -- 63.06 1568.55 s low bandwidth - enable, gain = 1, vdd=(3.3..5.5)v, overdrive=5 mv low to high, t = (-40+85)c -- 30.62 167.56 s high to low, t = (-40+85)c -- 33.54 181.40 s low bandwidth - disable, gain = 1, vdd=(3.3..5.5)v, overdrive=5 mv low to high, t = (-40+85)c -- 5.00 32.61 s high to low, t = (-40+85)c -- 5.24 33.88 s symbol parameter description/note conditions min. typ. max. unit
SLG46536_ds_105 page 20 of 164 SLG46536 g gain error (including threshold and internal vref error), t = (-40+85)c g = 1, vdd = 1.71 v vref = 501200 mv -- 1 -- g = 1, vdd = 3.3 v -- 1 -- g = 1, vdd = 5.5 v -- 1 -- g = 0.5, vdd = 1.71 v -1.00% -- 0.93% g = 0.5, vdd = 3.3 v -0.96% -- 0.82% g = 0.5, vdd = 5.5 v -1.04% -- 0.90% g = 0.33, vdd = 1.71v -1.75% -- 2.10% g = 0.33, vdd = 3.3 v -1.95% -- 1.69% g = 0.33, vdd = 5.5 v -2.03% -- 1.77% g = 0.25, vdd = 1.71v -1.91% -- 2.13% g = 0.25, vdd = 3.3 v -1.98% -- 1.80% g = 0.25, vdd = 5.5 v -2.12% -- 1.90% vref internal vref error, vref = 1200 mv vdd = 1.8 v 5 % t = 25c -0.58% -- 0.56% t = (-40+85)c -1.01% -- 0.70% vdd = 3.3 v 10 % t = 25c -0.59% -- 0.58% t = (-40+85)c -1.06% -- 0.72% vdd = 5.0 v 10 % t = 25c -0.64% -- 0.60% t = (-40+85)c -1.16% -- 0.74% internal vref error, vref = 1000 mv vdd = 1.8 v 5 % t = 25c -0.57% -- 0.58% t = (-40+85)c -1.14% -- 0.76% vdd = 3.3 v 10 % t = 25c -0.59% -- 0.58% t = (-40+85)c -1.04% -- 0.73% vdd = 5.0 v 10 % t = 25c -0.67% -- 0.64% t = (-40+85)c -1.15% -- 0.73% internal vref error, vref = 500 mv vdd = 1.8 v 5 % t = 25c -0.64% -- 0.64% t = (-40+85)c -1.11% -- 0.75% vdd = 3.3 v 10 % t = 25c -0.63% -- 0.63% t = (-40+85)c -1.10% -- 0.78% vdd = 5.0 v 10 % t = 25c -0.72% -- 0.70% t = (-40+85)c -1.15% -- 0.80% symbol parameter description/note conditions min. typ. max. unit
SLG46536_ds_105 page 21 of 164 SLG46536 6.0 summary of macrocell function 6.1 i/o pins ? digital input (low voltage or normal voltage, with or without schmitt trigger) ? open drain outputs ? push pull outputs ? analog i/o ? 10 k ? /100 k ? /1 m ?? pull-up/pull-down resistors ? 40 ma open drain 4x drive output 6.2 connection matrix ? digital matrix for circuit co nnections based on user design 6.3 analog compa rators (3 total) ? selectable hysteresis 0 m v / 25 mv / 50 mv / 200 mv ? wake and sleep control (part of combination function macrocell ) 6.4 voltage reference ? used for references on analog comparators 6.5 combination functi on macrocells (26 total) ? three selectable dff/latch or 2-bit luts ? one selectable continuous dff/latch or 3-bit lut ? eleven selectable dff/latch or 3-bit luts ? one selectable pipe delay or 3-bit lut ? one selectable programmable pa ttern generator or 2-bit lut ? five selectable 8-bit cnt/dly or 3-bit lut ? two selectable 16-bi t cnt/dly or 4-bit lut ? two deglitch filters with edge detectors 6.6 combinatinatorial logic macrocell ? one 4-bit lut 6.7 serial communications ?i 2 c protocol compliant 6.8 16x8 ram memory with def ined nvm otp initial state 6.9 pipe delay (part of combination function macrocell) ? 16 stage / 3 output ? one 1 stage fixed output ? two 1-16 stage se lectable outputs.
SLG46536_ds_105 page 22 of 164 SLG46536 6.10 programmable delay ? 125 ns/250 ns/375 ns/500 ns @ 3.3 v ? includes edge detection function 6.11 rc oscillator ? 25 khz and 2 mhz s electable frequency ? 25 mhz rc oscillator ? first stage divider (4): osc /1, osc/2, osc/4, and osc/8 ? second stage divider for 25 khz and 2 mhz (5): output to matri x: osc/1, osc/2, osc/3, osc/4, osc/8, osc/12, osc/24, osc/64 6.12 crystal oscillator
SLG46536_ds_105 page 23 of 164 SLG46536 7.0 i/o pins the SLG46536 has a total of 12 mu lti-function i/o pins which ca n function as either a user defined input or output, as well as serving as a special function, or serving as a signal for progr amming of the on-chip non volatile memory (nvm). refer to section 2.0 pin descripti on for normal and programming modepin definitions. normal mode pin definitions are as follows: ? pin 1: v dd power supply ? pin 2: general purpose input ? pin 3: general purpo se input or output ? pin 4: general purpose input or output or analog comparator 0( +) ? pin 5: general purpose input or output with oe or analog compa rator 0(-) ? pin 6: general purpose i nput or od output scl ? pin 7: general purpose i nput or od output sda ? pin 8: general purpose input or output with oe or analog compa rator 1(+) ? pin 9: ground ? pin 10: general purpose input or output or analog comparator 0 /1/2(-) ? pin 11: general purpose input or output with oe ? pin 12: general purpose input or output with oe ? pin 13: general purpose input or output or external clock input for osc0 25 khz/2 mhz ? pin 14: general purpose input or output or external clock inpu t for osc1 25 mhz programming mode pin definitions are as follows: ? pin 1: v dd power supply ? pin 2: v pp programming voltage ? pin 6: programming scl ? pin 7: programming sda ? pin 9: ground ? pin 12: programming mode control of the 12 user defined i/o pins on the SLG46536, all but one of the pins (pin 2) can serve as both digital input and digital o utput. pin 2 can only serve as a digital input pin. 7.1 input modes each i/o pin can be configured as a digital input pin with/with out buffered schmitt trigger, or can also be configured as a lo w voltage digital input. pins 4, 5 , 8 and10 can also be configure d to serve as analog inputs to the on-chip comparators. 7.2 output modes pins 3, 4, 5, 6, 7, 8, 10, 11, 1 2, 13 and 14 can all be configu red as digital output pins. 7.3 pull up/down resistors all i/o pins have the option for user selectable resistors conn ected to the input structure. th e selectable values on these re sistors are 10 k ? , 100 k ? and 1 m ? . in the case of pin 2, the resistors are fixed to a pull-down configuration. in the case of all other i/o pins, the internal resistors can be configured as either pull-u p or pull-downs.
SLG46536_ds_105 page 24 of 164 SLG46536 7.4 i/o register settings 7.4.1 pin 2 register settings pin 4 regist er settings pin 6 r egister settings table 15. pin 2 register settings signal function register bit address register definition pin 2 pull down resistor value selection <1029:1028> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 2 mode control <1031:1030> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved table 16. pin 3 register settings signal function register bit address register definition pin 3 driver strength selection <1041> 0: 1x 1: 2x pin 3 pull up/down resistor selection <1042> 0: pull down resistor 1: pull up resistor pin 3 pull up/down resistor value selection <1044:1043> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 3 mode control <1047:1045> 000 : digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved table 17. pin 4 register settings signal function register bit address register definition pin 4 driver strength selection <1057> 0: 1x 1: 2x pin 4 pull up/down resistor selection <1058> 0: pull down resistor 1: pull up resistor pin 4 pull up/down resistor value selection <1060:1059> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 4 mode control <1063:1061> 000 : digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain
SLG46536_ds_105 page 25 of 164 SLG46536 7.4.2 pin 5 re gister settings table 18. pin 5 register settings signal function register bit address register definition pin 5 pull up/down resistor selection <1065> 0: pull down resistor 1: pull up resistor pin 5 pull up/down resistor value selection <1067:1066> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 5 mode control (sig_pin5_oe =0) <1069:1068> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output pin 5 mode control (sig_pin5_oe =1) <1071:1070> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x
SLG46536_ds_105 page 26 of 164 SLG46536 7.4.3 pin 6 re gister settings 7.4.4 pin 7 re gister settings table 19. pin 6 register settings signal function register bit address register definition pin 6 driver strength selection <1073> 0: 1x 1: 2x sele ct sc l & virt ua l input 0 or pin6 <1074> 0: scl & virtual input 0 1: pin6 pin 6 pull down resistor value selection <1076:1075> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 6 mode control <1079:1077> 000 : digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: reserved 101: open drain nmos 110: reserved 111: reserved table 20. pin 7 register settings signal function register bit address register definition pin 7 (or sda) driver strength selection <1081> 0: 1x 1: 2x select sda & virtual input 1 or pin7 <1082> 0: sda & virtual input 1 1: pin7 pin 7 pull down resistor value selection <1084:1083> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 7(or sda) mode control <1087:1085> 000: digital i nput without sc hmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: reserved 101: open drain nmos 110: reserved 111: reserved
SLG46536_ds_105 page 27 of 164 SLG46536 7.4.5 pin 8 re gister settings 7.4.6 pin 10 register settings table 21. pin 8 register settings signal function register bit address register definition pin 8 4x drive (4x, nmos open drain) selection <1088> 0: 4x drive off 1: 4x drive on (sig_pin 8_oe=1 & reg <1095:1094> = 1x) pin 8 pull up/down resistor selection <1089> 0: pull down resistor 1: pull up resistor pin 8 pull up/down resistor value selection <1091:1090> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 8 mode control (sig_pin8_oe =0) <1093:1092> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output pin 8 mode control (sig_pin8_oe =1) <1095:1094> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x table 22. pin 10 register settings signal function register bit address register definition pin 10 4x drive (4x, nmos open drain) selection <1096> 0: 4x drive off 1: 4x drive on (r eg <1095:1094> = 1x) pin 10 driver strength selection <1097> 0: 1x 1: 2x pin 10 pull up/down resistor selection <1098> 0: pull down resistor 1: pull up resistor pin 10 pull up/down resistor value selection <1100:1099> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 10 mode control <1103:1101> 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain
SLG46536_ds_105 page 28 of 164 SLG46536 7.4.7 pin 11 register settings 7.4.8 pin 12 register settings table 23. pin 11 register settings signal function register bit address register definition pin 11 pull up/down resistor selection <1113> 0: pull down resistor 1: pull up resistor pin 11 pull up/down resistor value selection <1115:1114> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 11 mode control (sig_pin11_oe =0) <1117:1116> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved pin 11 mode control (sig_pin11_oe =1) <1119:1118> 00: push pull 1x 01: push pull 2x 10: reserved 11: reserved table 24. pin 12 register settings signal function register bit address register definition pin 12 pull up/down resistor selection <1129> 0: pull down resistor 1: pull up resistor pin 12 pull up/down resistor value selection <1131:1130> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 12 mode control (sig_pin12_oe =1) <1135:1134> 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x pin 12 mode control (sig_pin12_oe =0) <1133:1132> 00: digital input without schmitt trigger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved
SLG46536_ds_105 page 29 of 164 SLG46536 7.4.9 pin 13 register settings 7.4.10 pin 14 register settings table 25. pin 13 register settings signal function register bit address register definition pin 13 driver strength selection <1137> 0: 1x 1: 2x pin 13 pull up/down resistor selection <1138> 0: pull down resistor 1: pull up resistor pin 13 pull up/down resistor value selection <1140:1139> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 13 mode control <1143:1141> 000: digital i nput without sc hmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved table 26. pin 14 register settings signal function register bit address register definition pin 14 driver strength selection <1161> 0: 1x 1: 2x pin 14 pull up/down resistor selection <1162> 0: pull down resistor 1: pull up resistor pin 14 pull up/down resistor value selection <1164:1163> 00: floating 01: 10 k ? resistor 10: 100 k ? resistor 11: 1 m ? resistor pin 14 mode control <1167:1165> 000: digital i nput without sc hmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: reserved
SLG46536_ds_105 page 30 of 164 SLG46536 7.5 gpi structure 7.5.1 gpi structure (for pin 2) figure 2. pin 2 gpi s tructure diagram digital in low voltage input non-schmitt trigger input oe lv_en schmitt trigger input oe smt_en oe wosmt_en pad s0 s1 s2 s3 floating 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1, oe=0 01: digital in with schmit t trigger, smt_en=1, oe=0 10: low voltage digital in mode, lv_en = 1, oe=0 11: reserved note 1: oe cannot be selected by user note 2: oe is matrix output , digital in is matrix input
SLG46536_ds_105 page 31 of 164 SLG46536 7.6 matrix oe io structure 7.6.1 matrix oe io structu re (for pins 5, 11, 12) figure 3. matrix oe io structure diagram pad s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1 01: digital in with schm itt trigger, smt_en=1 10: low voltage digital in mode, lv_en = 1 11: analog io mode output mode [1:0] 00: 1x push-pull mode, pp1x_en=1 01: 2x push-pull mode, pp2x_en=1, pp1x_en=1 10: 1x nmos open drain mode, od1x_en=1(except pin11) 11: 2x nmos open drain mode, od2x_en=1, od1x_en=1(except pin11) note: digital out and o e are matrix output , digital in is matri x input (for pin 5 only) digital out digital out oe od2x_en oe od1x_en digital out oe pp2x_en digital out oe pp1x_en digital in low voltage input non-schmitt trigger input analog io oe lv_en schmitt trigger input oe smt_en oe wosmt_en
SLG46536_ds_105 page 32 of 164 SLG46536 7.6.2 matrix oe io struc ture (for pi ns 6 and 7) figure 4. matrix oe io structure diagram pad s0 s1 s2 s3 floating 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? pin 6, pin 7mode [2:0] 000: digital input without schmitt trigger 001: digital input with schmitt trigger 010: low voltage digital input 011: reserved 100: reserved 101: open drain nmos 110: reserved 111: reserved note: digital out and oe are matrix output, digital in is matri x input digital out oe od1x_en digital in low voltage input non-schmitt trigger input oe lv_en schmitt trigger input oe smt_en oe wosmt_en
SLG46536_ds_105 page 33 of 164 SLG46536 7.6.3 matrix oe 4x driv e structure (for pin 8) figure 5. matrix oe io 4x drive structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? low voltage input non-schmitt trigger input input mode [1:0] 00: digital in without schmitt trigger, wosmt_en=1 01: digital in with schmitt trigger, smt_en=1 10: low voltage digital in mode, lv_en = 1 11: analog io mode output mode [1:0] 00: 1x push-pull mode, pp1x_en=1 01: 2x push-pull mode, pp2x_en=1, pp1x_en=1 10: 1x nmos open drain mode, od1x_en=1, odn_en=1 11: 2x nmos open drain mode, od2x_en=1, od1x_en=1, odn_en=1 note: digital out and oe are matrix output, digital in is matri x input analog io digital out digital out oe oe digital out oe pp2x_en digital out oe pp1x_en oe lv_en schmitt trigger input oe smt_en oe wosmt_en odn_en od1x_en 4x_en oe digital out od2x_en 4x_en odn_en odn_en 4x_en digital out oe odn_en 4x_en
SLG46536_ds_105 page 34 of 164 SLG46536 7.6.4 4x drive str ucture (for pin 10) figure 6. io 4x drive structure diagram pad digital in s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? low voltage input non-schmitt trigger input analog io digital out digital out oe oe digital out oe pp2x_en digital out oe pp1x_en oe lv_en schmitt trigger input oe smt_en oe wosmt_en odn_en od1x_en 4x_en oe digital out od2x_en 4x_en odn_en odn_en 4x_en digital out oe odn_en 4x_en mode [2:0] 000: digital in without schmitt trigger, wosmt_en=1, oe = 0 001: digital in with schmitt trigger, smt_en=1, oe = 0 010: low voltage digital in mode, lv_en = 1, oe = 0 011: analog io mode 100: push-pull mode, pp_en=1, oe = 1 101: nmos open drain mode, odn_en=1, oe = 1 110: pmos open drain mode, odp_en=1, oe = 1 111: analog io and nmos open-drain mode, odn_en=1 and aio_en=1 note 1: oe cannot be selected by user note 2: digital out and oe are matrix output, digital in is mat rix input
SLG46536_ds_105 page 35 of 164 SLG46536 7.7 io structure 7.7.1 io structure (fo r pins 3, 4, 13, 14) figure 7. io structure diagram pad s0 s1 s2 s3 floating s0 s1 pull_up_en 10 k ? 90 k ? 900 k ? res_sel[1:0] 00: floating 01: 10 k ? 10: 100 k ? 11: 1 m ? mode [2:0] 000: digital in without schmitt trigger, wosmt_en=1, oe = 0 001: digital in with schmitt trigger, smt_en=1, oe = 0 010: low voltage digital in mode, lv_en = 1, oe = 0 011: analog io mode 100: push-pull mode, pp_en=1, oe = 1 101: nmos open drain mode, odn_en=1, oe = 1 110: pmos open drain mode, odp_en=1, oe = 1 111: analog io and nmos open-drain mode, odn_en=1 and aio_en=1 note: oe cannot be selected by user and is controlled by regist er digital out digital out oe odn_en oe odn_en digital out oe 2x_en pp_en 2x_en odp_en digital out oe pp_en 2x_en odp_en digital in low voltage input non-schmitt trigger input analog io (for pin 4 only) oe lv_en schmitt trigger input oe smt_en oe wosmt_en
SLG46536_ds_105 page 36 of 164 SLG46536 8.0 connection matrix the connection matrix in the SLG46536 is used to create the int ernal routing for internal functional macrocells of the device once it is programmed. the registers are programmed from the one-tim e nvm cell during test mode operation. the output of each functional macrocell within the SLG46536 has a specific digital bit code assigned to it that is either set to active high or inactive low based on the design that is created. once the 2048 regist er bits within the SLG46536 are programmed a fully custom circu it will be created. the connection matrix has 64 inputs and 110 outputs. each of th e 64 inputs to the connection matrix is hard-wired to the digit al output of a particular source ma crocell, including i/o pins, lu ts, analog comparators, other d igital resources and vdd and gnd . the input to a digital macrocell uses a 6-bit register to selec t one of these 64 input lines. for a complete list of the slg 46536s register t able, see secti on 20.0 appendix a - slg465 36 register definition. figure 8. connection matrix figure 9. connection matrix example gnd 0 pin 2 digital in 1 pin 3 digital in 2 pin 4 digital in 3 matrix input signal functions n resetb_core 62 vdd 63 n function registers 109 matrix out: pd of xtal osc reg<877:872> 0 matrix out: in0 of lut3_11 or clk input of dff8 reg<5:0> 1 matrix out: in1 of lut3_11 or data input of dff8 reg<13:8> 2 matrix out: in2 of lut3_11 or rstb (setb) of dff8 reg<21:16> matrix inputs matrix outputs pin 10 pin 9 pin 11 connection matrix lut pin 10 pin 9 lut pin 11 function
SLG46536_ds_105 page 37 of 164 SLG46536 8.1 matrix input table table 27. matrix input table matrix input number matrix input signal function matrix decode 5 4 3 2 1 0 0 gnd 000000 1 pin2 digital input 0 0 0 0 0 1 2 reserved 000010 3 pin3 digital input 0 0 0 0 1 1 4 reserved 000100 5 pin4 digital input 0 0 0 1 0 1 6 pin5 digital input 0 0 0 1 1 0 7 pin8 digital input 0 0 0 1 1 1 8 lut2_0 / dff0 output 0 0 1 0 0 0 9 lut2_1 / dff1 output 0 0 1 0 0 1 10 lut2_2 / dff2 output 0 0 1 0 1 0 11 lut2_3 / pgen output 0 0 1 0 1 1 12 lut3_0 / dff3 (set/rst) output 0 0 1 1 0 0 13 lut3_1 / dff4 (set/rst) output 0 0 1 1 0 1 14 lut3_2 / dff5 (set/rst) output 0 0 1 1 1 0 15 lut3_3 / dff6 (set/rst) output 0 0 1 1 1 1 16 lut3_4 / dff7 (set/rst) output 0 1 0 0 0 0 17 lut3_5 / cnt_dly2(8bit) output 0 1 0 0 0 1 18 lut3_6 / cnt_dly3(8bit) output 0 1 0 0 1 0 19 lut3_7 / cnt_dly4(8bit) output 0 1 0 0 1 1 20 lut3_8 / cnt_dly5(8bit) output 0 1 0 1 0 0 21 lut3_9 / cnt_dly6(8bit) output 0 1 0 1 0 1 22 lut4_0 / cnt_dly0(16bit) output 0 1 0 1 1 0 23 lut4_1 / cnt_dly1(16bit) output 0 1 0 1 1 1 24 lut3_10 / pipe delay ( 1st stage) output 0 1 1 0 0 0 25 pipe delay output0 0 1 1 0 0 1 26 pipe delay output1 0 1 1 0 1 0 27 internal osc post-divided by 1/2/3/4/8/12/24/64 output (25khz/2mhz) 011011 28 internal osc post-divided by 1/2/3/4/8/12/24/64 output (25khz/2mhz) 011100 29 internal osc pre-divided by 1/ 2/4/8 output ( 25 mhz) 011101 30 filter0 / edge det ect0 output 0 1 1 1 1 0 31 filter1 / edge det ect1 output 0 1 1 1 1 1 32 pin6 digital or i2c_virtual_0 input 1 0 0 0 0 0 33 pin7 digital or i2c_virtual_1 input 1 0 0 0 0 1 34 i2c_virtual_2 input 1 0 0 0 1 0 35 i2c_virtual_3 input 1 0 0 0 1 1
SLG46536_ds_105 page 38 of 164 SLG46536 36 i2c_virtual_4 input 1 0 0 1 0 0 37 i2c_virtual_5 input 1 0 0 1 0 1 38 i2c_virtual_6 input 1 0 0 1 1 0 39 i2c_virtual_7 input 1 0 0 1 1 1 40 lut3_11 / dff8 (set/rst) output 1 0 1 0 0 0 41 lut3_12 / dff9 (set/rst) output 1 0 1 0 0 1 42 lut3_13 / dff10 (set/rst) output 1 0 1 0 1 0 43 lut3_14 / dff11 (set/rst) output 1 0 1 0 1 1 44 lut3_15 / dff12 (set/rst) output 1 0 1 1 0 0 45 lut3_16 / dff13 (set/rst) output 1 0 1 1 0 1 46 lut3_17 / dff14 (set/rst) output 1 0 1 1 1 0 47 lut4_2 output 1 0 1 1 1 1 48 pin10 digital input 1 1 0 0 0 0 49 reserved 110001 50 pin11 digital input 1 1 0 0 1 0 51 reserved 110011 52 pin12 digital input 1 1 0 1 0 0 53 pin13 digital input 1 1 0 1 0 1 54 reserved 110110 55 reserved 110111 56 pin14 digital input 1 1 1 0 0 0 57 acmp_0 output 1 1 1 0 0 1 58 acmp_1 output 1 1 1 0 1 0 59 acmp_2 output 1 1 1 0 1 1 60 reserved 111100 61 programmable delay with e dge detector output 1 1 1 1 0 1 62 resetb_core (por) as matrix input 1 1 1 1 1 0 63 vdd 111111 table 27. matrix input table matrix input number matrix input signal function matrix decode 5 4 3 2 1 0
SLG46536_ds_105 page 39 of 164 SLG46536 8.2 matrix output table table 28. matrix output table register bit address matrix output signal function note: for each address, the two m ost significant bits are unuse d) matrix output number reg <7:0> matrix out: in0 of l ut3_11 or clock input of dff8 0 reg <15:8> matrix out: in1 of lut3_11 or data input of dff8 1 reg <23:16> matrix out: in2 of lut3_11 or rstb (setb) of dff8 2 reg <31:24> matrix out: in0 of l ut3_12 or clock input of dff9 3 reg <39:32> matrix out: in1 of l ut3_12 or data input of dff9 4 reg <47:40> matrix out: in2 of l ut3_12 or rstb (setb) of dff9 5 reg <55:48> matrix out: in0 of l ut3_13 or clock input of dff10 6 reg <63:56> matrix out: in1 of l ut3_13 or data input of dff10 7 reg <71:64> matrix out: in2 of l ut3_13 or rstb ( setb) of dff10 8 reg <79:72> matrix out: in0 of l ut3_14 or clock input of dff11 9 reg <87:80> matrix out: in1 of l ut3_14 or data input of dff11 10 reg <95:88> matrix out: in2 of l ut3_14 or rstb ( setb) of dff11 11 reg <103:96> matrix out: in0 of l ut3_15 or clock input of dff12 1 2 reg <111:104> matrix out: in1 of l ut3_15 or data input of dff12 1 3 reg <119:112> matrix out: in2 of lut3_15 or rstb (setb) of dff12 14 reg <127:120> matrix out: in0 o f lut3_16 or clock input of dff13 15 reg <135:128> matrix out: in1 of l ut3_16 or data input of dff13 1 6 reg <143:136> matrix out: in2 of lut3_16 or rstb (setb) of dff13 17 reg <151:144> matrix out: in0 o f lut3_17 or clock input of dff14 18 reg <159:152> matrix out: in1 of l ut3_17 or data input of dff14 1 9 reg <167:160> matrix out: in2 of lut3_17 or rstb (setb) of dff14 20 reg <175:168> matrix out: in0 of lut4_2 21 reg <183:176> matrix out: in1 of lut4_2 22 reg <191:184> matrix out: in2 of lut4_2 23 reg <199:192> matrix out: in3 of lut4_2 24 reg <207:200> reserved 25 reg <215:208> reserved 26 reg <223:216> matrix out: pi n3 digital output source 27 reg <231:224> reserved 28 reg <239:232> reserved 29 reg <247:240> matrix out: pi n4 digital output source 30 reg <255:248> matrix out: pi n5 digital output source 31 reg <263:256> matrix out : pin5 output enable 32 reg <271:264> matrix out: pin6 dig ital output source (scl with v i/input & nmos open-drain) 33 reg <279:272> matrix out: pin7 dig ital output source (sda with v i/input & nmos open-drain) 34 reg <287:280> matrix out: pi n8 digital output source 35 reg <295:288> matrix out : pin8 output enable 36 reg <303:296> matrix out: pin1 0 digital output source 37
SLG46536_ds_105 page 40 of 164 SLG46536 reg <311:304> reserved 38 reg <319:312> reserved 39 reg <327:320> matrix out: pin1 1 digital output source 40 reg <335:328> matrix out: pin11 output enable 41 reg <343:336> reserved 42 reg <351:344> matrix out: pin1 2 digital output source 43 reg <359:352> matrix out: pin12 output enable 44 reg <367:360> matrix out: pin1 3 digital output source 45 reg <375:368> reserved 46 reg <383:376> reserved 47 reg <391:384> reserved 48 reg <399:392> reserved 49 reg <407:400> matrix out: pin1 4 digital output source 50 reg <415:408> matrix out: acmp0 pdb (power down) 51 reg <423:416> matrix out: acmp1 pdb (power down) 52 reg <431:424> matrix out: acmp2 pdb (power down) 53 reg <439:432> reserved 54 reg <447:440> matrix out: input of filter_0 with fixed time edge detector 55 reg <455:448> matrix out: input of filter_1 with fixed time edge detector 56 reg <463:456> matrix out: input of programmable delay & edge det ector 57 reg <471:464> matrix out: osc 25 khz/2 mhz pdb (power down) 58 reg <479:472> matrix out: os c 25 mhz pdb (power down) 59 reg <487:480> matrix out: in0 o f lut2_0 or clock input of dff0 60 reg <495:488> matrix out: in1 o f lut2_0 or data input of dff0 61 reg <503:496> matrix out: in0 o f lut2_1 or clock input of dff1 62 reg <511:504> matrix out: in1 o f lut2_1 or data input of dff1 63 reg <519:512> matrix out: in0 o f lut2_2 or clock input of dff2 64 reg <527:520> matrix out: in1 o f lut2_2 or data input of dff2 65 reg <535:528> matrix out: in0 o f lut2_3 or clock input of pgen 66 reg <543:536> matrix out: in1 of lut2_3 or rstb of pgen 67 reg <551:544> matrix out: in0 o f lut3_0 or clock input of dff3 68 reg <559:552> matrix out: in1 o f lut3_0 or data input of dff3 69 reg <567:560> matrix out: in2 o f lut3_0 or rstb (setb) of dff3 70 reg <575:568> matrix out: in0 o f lut3_1 or clock input of dff4 71 reg <583:576> matrix out: in1 o f lut3_1 or data input of dff4 72 reg <591:584> matrix out: in2 o f lut3_1 or rstb (setb) of dff4 73 reg <599:592> matrix out: in0 o f lut3_2 or clock input of dff5 74 reg <607:600> matrix out: in1 o f lut3_2 or data input of dff5 75 reg <615:608> matrix out: in2 o f lut3_2 or rstb (setb) of dff5 76 table 28. matrix output table register bit address matrix output signal function note: for each address, the two m ost significant bits are unuse d) matrix output number
SLG46536_ds_105 page 41 of 164 SLG46536 reg <623:616> matrix out: in0 o f lut3_3 or clock input of dff6 77 reg <631:624> matrix out: in1 o f lut3_3 or data input of dff6 78 reg <639:632> matrix out: in2 o f lut3_3 or rstb (setb) of dff6 79 reg <647:640> matrix out: in0 o f lut3_4 or clock input of dff7 80 reg <655:648> matrix out: in1 o f lut3_4 or data input of dff7 81 reg <663:656> matrix out: in2 o f lut3_4 or rstb (setb) of dff7 82 reg <671:664> matrix out: in0 of lut3_5 or delay2 input (or coun ter2 rst input) 83 reg <679:672> matrix out: in1 o f lut3_5 or external clock input of delay2 (or counter2) 84 reg <687:680> matrix out: in2 of lut3_5 85 reg <695:688> matrix out: in0 of lut3_6 or delay3 input (or coun ter3 rst input) 86 reg <703:696> matrix out: in1 o f lut3_6 or external clock input of delay3 (or counter3) 87 reg <711:704> matrix out: in2 of lut3_6 88 reg <719:712> matrix out: in0 of lut3_7 or delay4 input (or coun ter4 rst input) 89 reg <727:720> matrix out: in1 o f lut3_7 or external clock input of delay4 (or counter4) 90 reg <735:728> matrix out: in2 of lut3_7 91 reg <743:736> matrix out: in0 of lut3_8 or delay5 input (or coun ter5 rst input) 92 reg <751:744> matrix out: in1 o f lut3_8 or external clock input of delay5 (or counter5) 93 reg <759:752> matrix out: in2 of lut3_8 94 reg <767:760> matrix out: in0 of lut3_9 or delay6 input (or coun ter6 rst input) 95 reg <775:768> matrix out: in1 o f lut3_9 or external clock input of delay6 (or counter6) 96 reg <783:776> matrix out: in2 of lut3_9 97 reg <791:784> matrix out: in0 o f lut3_10 or input of pipe delay 9 8 reg <799:792> matrix out: in1 of lut3_10 or rstb of pipe delay 99 reg <807:800> matrix out: in2 of lut3_10 or clock of pipe delay 1 00 reg <815:808> matrix out: in0 of lut4_0 or delay0 input (or coun ter0 rst/set input) 101 reg <823:816> matrix out: in1 o f lut4_0 or external clock input of delay0 (or counter0) 102 reg <831:824> matrix out: in2 o f lut4_0 or up input of fsm0 103 reg <839:832> matrix out: in3 o f lut4_0 or keep input of fsm0 104 reg <847:840> matrix out: in0 of lut4_1 or delay1 input (or coun ter1 rst/set input) 105 reg <855:848> matrix out: in1 o f lut4_1 or external clock input of delay1 (or counter1) 106 reg <863:856> matrix out: in2 o f lut4_1 or up input of fsm1 107 reg <871:864> matrix out: in3 o f lut4_1 or keep input of fsm1 108 reg <879:872> matrix out: pd of crystal oscillator by reg<1268> 109 table 28. matrix output table register bit address matrix output signal function note: for each address, the two m ost significant bits are unuse d) matrix output number
SLG46536_ds_105 page 42 of 164 SLG46536 8.3 connection matrix virtual inputs as mentioned previously, the conn ection matrix inputs come from the outputs of various digital m acrocells on the device. eight of the connection matrix inputs have the special characteristic that the state of these signal lines comes from a correspondin g data bit written as a register value via i 2 c. this gives the user the ability to write data via the serial channel, and have this information translated into sig nals that can be driven into the connection matrix and from the connection matrix to the digita l inputs of other macrocell s on the device. the i 2 c address for reading and writing these regist er values is at b yte 0244. six of the eight connection matr ix virtual inputs are dedicated to this virtual input function. an i 2 c write command to these register bits will set the signal values going into the connection matri x to the desired state. a read command to these register bits w ill read either the original data values coming from the nvm memory bits (that were loaded during the initial device startup), or the v alues from a previous write command (if that has happened). two of the eight connection matrix virtual inputs are shared wi th pin digital inputs,(pin8 digital or i2c_virtual_0 input) and (pin9 digital or i2c_virtual_1 input). if the virtual input mode is s elected, an i 2 c write command to these register bits will set the signal values going into the connection matrix to the desired state. a read command to these register bits will read either the origi nal data values coming from the nvm memory bits (that were loaded d uring the initial device startup ), or the values from a previou s write command (if that has happen ed). two register bits select whether the connection matrix in put comes from the pin input or from the virtual register: ? reg <1074> select scl & v irtual input 0 or pin6 ? reg <1082> select sda & v irtual input 1 or pin7 see table below for connecti on matrix virtual inputs. 8.4 connection matrix virtual outputs the digital outputs of the various macrocells are routed to the connection matrix to enable interconnections to the inputs of other macrocells in the device. at the same time, it is possible to r ead the state of each of the macrocell outputs as a register va lue via i 2 c. this option, called connecti on matrix virtual outputs, allow s the user to remotely read the values of each macrocell output . the i 2 c addresses for reading these register values are at bytes 0240 to 0247. write commands to these same register values will be ignored (with the exception of the virtual input regist er bits at byte 0244). matrix input number matrix input signal function register bit addresses (d) 32 i2c_virtual_0 input reg<1952> 33 i2c_virtual_1 input reg<1953> 34 i2c_virtual_2 input reg<1954> 35 i2c_virtual_3 input reg<1955> 36 i2c_virtual_4 input reg<1956> 37 i2c_virtual_5 input reg<1957> 38 i2c_virtual_6 input reg<1958> 39 i2c_virtual_7 input reg<1959>
SLG46536_ds_105 page 43 of 164 SLG46536 9.0 combination function macrocells the SLG46536 has twenty-four com bination function macrocells th at can serve more than one log ic or timing function. in each case, they can serve as a look up table (lut), or as another lo gic or timing function. see the list below for the functions th at can be implemented in these macrocells: ? three macrocells that can serve as either 2-bit luts or as d f lip flops; ? twelve macrocells that can serve as either 3-bit luts or as d flip flops with set/reset input; ? one macrocell that can serve as either 3-bit lut or as pipe de lay; ? one macrocell that can serve as either 2-bit lut or as program mable pattern generator (pgen); ? five macrocells that can serve as either 3-bit luts or as 8-bi t counter / delays; ? two macrocells that can serve as either 4-bit luts or as 16-bi t counter / delays. inputs/outputs for the 24 combi nation function macrocells are c onfigured from the connection matrix with specific logic functi ons being defined by the state of nvm bits. when used as a lut to implement combinatorial logic functions, the outputs of the luts can be configured to any user defined function, including th e following standard digital logic device s (and, nand, or, nor, xor, xnor). 9.1 2-bit lut or d flip flop macrocells there are three macrocells that c an serve as either 2-bit luts or as d flip flops. when used to implement lut functions, the 2-bit luts each take in two input signals from the connection m atrix and produce a single output, which goes back into the connection matrix. when used to implement d flip flop function, the two input signals from the connection matrix go to the dat a (d) and clock (clk) inputs for t he flip flop, with the output g oing back to the connection matrix. the operation of the d flip-flop and latch will follow the func tional descriptions below: dff: clk is rising edge triggered , then q = d; otherwise q will not change. latch: when clk is low, then q = d; otherwise q remains its pre vious value (input d has no effect on the output, when clk is high) figure 10. 2-bit lut0 or dff0 dff0 clk d 2-bit lut0 out in0 in1 to connection matrix input <8> 4-bits nvm from connection matrix output <61> 1-bit nvm reg <1207:1204> reg <1191> from connection matrix output <60> q/nq reg <1207> dff or latch select reg <1206> output select (q or nq) reg <1205> dff initial polarity select lut truth table dff registers s0 s1 s0 s1 s0 s1 0: 2-bit lut0 in0 1: dff0 clk 0: 2-bit lut0 in1 1: dff0 data 0: 2-bit lut0 out 1: dff0 out
SLG46536_ds_105 page 44 of 164 SLG46536 figure 11. 2-bit lut1 or dff1 figure 12. 2-bit lut2 or dff2 dff1 clk d 2-bit lut1 out in0 in1 to connection matrix input <9> 4-bits nvm from connection matrix output <63> 1-bit nvm reg <1203:1200> reg <1190> from connection matrix output <62> q/nq reg <1203> dff or latch select reg <1202> output select (q or nq) reg <1201> dff initial polarity select lut truth table dff registers s0 s1 s0 s1 s0 s1 0: 2-bit lut1 in0 1: dff1 clk 0: 2-bit lut1 in1 1: dff1 data 0: 2-bit lut1 out 1: dff1 out dff2 clk d 2-bit lut2 out in0 in1 to connection matrix input <10> 4-bits nvm from connection matrix output <65> 1-bit nvm reg <1215:1212> reg <1189> from connection matrix output <64> q/nq reg <1215> dff or latch select reg <1214> output select (q or nq) reg <1213> dff initial polarity select lut truth table dff registers s0 s1 s0 s1 s0 s1 0: 2-bit lut2 in0 1: dff2 clk 0: 2-bit lut2 in1 1: dff2 data 0: 2-bit lut2 out 1: dff2 out
SLG46536_ds_105 page 45 of 164 SLG46536 9.1.1 2-bit lut or d flip flop macrocells used as 2-bit luts each macrocell, when programmed for a lut function, uses a 4-bi t register to define their output function: 2-bit lut0 is defined by reg<1207:1204> 2-bit lut1 is defined by reg<1203:1200> 2-bit lut2 is defined by reg<1215:1212> the table below shows the regist er bits for the standard digita l logic devices (and, nand, or , nor, xor, xnor) that can be created within each of the t wo 2-bit lut logic cells. table 32. 2-bit lut stand ard digital functions function msb lsb and-2 1000 nand-2 0 1 1 1 or-2 1110 nor-2 0 0 0 1 xor-2 0110 xnor-2 1001 table 29. 2-bit lut0 truth table in1 in0 out 0 0 reg <1204> lsb 0 1 reg <1205> 1 0 reg <1206> 1 1 reg <1207> msb table 30. 2-bit lut1 truth table in1 in0 out 0 0 reg <1200> lsb 0 1 reg <1201> 1 0 reg <1202> 1 1 reg <1203> msb table 31. 2-bit lut2 truth table in1 in0 out 0 0 reg <1212> lsb 0 1 reg <1213> 1 0 reg <1214> 1 1 reg <1215> msb
SLG46536_ds_105 page 46 of 164 SLG46536 9.1.2 2-bit lut or d flip flop macrocells used as d flip flop register se ttings table 33. dff0 register settings signal function register bit address register definition lut2_0 or dff0 select <1191> 0: lut2_0 1: dff0 dff0 initial polarity select <1205> 0: low 1: high dff0 output select <1206> 0: q output 1: nq output dff0 or latch select <1207> 0: dff function 1: latch function table 34. dff1 register settings signal function register bit address register definition lut2_1 or dff1 select <1190> 0: lut2_1 1: dff1 dff1 initial polarity select <1201> 0: low 1: high dff1 output select <1202> 0: q output 1: nq output select or latch select <1203> 0: dff function 1: latch function table 35. dff2 register settings signal function register bit address register definition lut2_2 or dff2 select <1189> 0: lut2_2 1: dff2 dff2 initial polarity select <1213> 0: low 1: high dff2 output select <1214> 0: q output 1: nq output dff2 or latch select <1215> 0: dff function 1: latch function
SLG46536_ds_105 page 47 of 164 SLG46536 9.2 3-bit lut or d flip flop with set/reset macrocells there are twelve macrocells that can serve as either 3-bit luts or as d flip flops with set/reset inputs. when used to impleme nt lut functions, the 3-bit luts each take in three input signals from the connection matrix and produce a single output, which g oes back into the connection matrix. when used to implement d flip flop function, the three input signals from the connection matr ix go to the data (d) and clock (clk) and set/reset (nrst/nset) in puts for the flip flop, with the output going back to the conne ction matrix. dff3 is a selectable continious d ff latch, it has an option tha t allows the macrocell output to either come from the q/nq outp ut of one d flip flop, or two d flip flops in series, with the fir st d flip flop triggering on the rising clock edge, and the sec ond d flip flop triggering on the falling clock edge. figure 13. dff polarity operations
SLG46536_ds_105 page 48 of 164 SLG46536 figure 14. 3-bit lut0 or dff3 with rst/set figure 15. 3-bit lut1 or dff4 with rst/set dff3 clk d to connection matrix< input 12> 8-bits nvm from connection matrix output <70> 1-bit nvm 3-bit lut0 out in1 in2 in0 nrst/nset from connection matrix output <69> from connection matrix output <68> reg <1223:1216> reg <1187> reg <1471> selects output from one or two dff q/nq ddq q reg <1222> reg <1471> lut truth tab l e reg <1223> dff or latch select reg <1222> output select (q or nq) reg <1221> dff nrst or nset select reg <1220> dff initial polarity select 0: 3-bit lut0 in1 1: dff3 d 0: 3-bit lut0 in2 1: dff3 nrst/nset 0: 3-bit lut0 out 1: dff3 out 0: 3-bit lut0 in0 1: dff3 clk s0 s1 s0 s1 s0 s1 s0 s1 dff4 clk d 8-bits nvm 1-bit nvm 3-bit lut1 out in1 in2 in0 nrst/nset from connection matrix output <73> from connection matrix output <72> from connection matrix output <71> reg <1231:1224> reg <1186> to connection matrix input <13> q/nq reg <1231> dff or latch select reg <1230> output select (q or nq) reg <1229> dff nrst or nset select reg <1228> dff initial polarity select lut truth tab l e dff registers 0: 3-bit lut1 in1 1: dff4 d 0: 3-bit lut1 in2 1: dff4 nrst/nset 0: 3-bit lut1 out 1: dff4 out 0: 3-bit lut1 in0 1: dff4 clk s0 s1 s0 s1 s0 s1 s0 s1
SLG46536_ds_105 page 49 of 164 SLG46536 figure 16. 3-bit lut2 or dff5 with rst/set figure 17. 3-bit lut3 or dff6 with rst/set dff5 clk d to connection matrix input <14> 8-bits nvm from connection matrix output <76> 1-bit nvm 3-bit lut2 out in1 in2 in0 nrst/nset from connection matrix output <75> from connection matrix output <74> reg <1239:1232> reg <1185> q/nq reg <1239> dff or latch select reg <1238> output select (q or nq) reg <1237> dff nrst or nset select reg <1236> dff initial polarity select lut truth table dff registers 0: 3-bit lut2 in1 1: dff5 d 0: 3-bit lut2 in2 1: dff5 nrst/nset 0: 3-bit lut2 out 1: dff5 out 0: 3-bit lut2 in0 1: dff5 clk s0 s1 s0 s1 s0 s1 s0 s1 dff6 clk d 8-bits nvm 1-bit nvm 3-bit lut3 out in1 in2 in0 nrst/nset from connection matrix output <79> from connection matrix output <78> from connection matrix output <77> reg <1247:1240> reg <1184> to connection matrix input <15> q/nq reg <1247> dff or latch select reg <1246> output select (q or nq) reg <1245> dff nrst or nset select reg <1244> dff initial polarity select lut truth tab l e dff registers 0: 3-bit lut3 in1 1: dff6 d 0: 3-bit lut3 in2 1: dff6 nrst/nset 0: 3-bit lut3 out 1: dff6 out 0: 3-bit lut3 in0 1: dff6 clk s0 s1 s0 s1 s0 s1 s0 s1
SLG46536_ds_105 page 50 of 164 SLG46536 figure 18. 3-bit lut4 or dff7 with rst/set figure 19. 3-bit lut11 or dff8 with rst/set dff7 clk d to connection matrix input <16> 8-bits nvm from connection matrix output <82> 1-bit nvm 3-bit lut4 out in1 in2 in0 nrst/nset from connection matrix output <81> from connection matrix output <80> reg <1255:1248> reg <1199> q/nq reg <1255> dff or latch select reg <1254> output select (q or nq) reg <1253> dff nrst or nset select reg <1252> dff initial polarity select lut truth table dff registers 0: 3-bit lut4 in1 1: dff7 d 0: 3-bit lut4 in2 1: dff7 nrst/nset 0: 3-bit lut4 out 1: dff7 out 0: 3-bit lut4 in0 1: dff7 clk s0 s1 s0 s1 s0 s1 s0 s1 dff8 clk d to connection matrix input <40> 8-bits nvm from connection matrix output <2> 1-bit nvm 3-bit lut11 out in1 in2 in0 nrst/nset from connection matrix output <1> from connection matrix output <0> reg <1375:1368> reg <1367> q/nq reg <1375> dff or latch select reg <1374> output select (q or nq) reg <1373> dff nrst or nset select reg <1372> dff initial polarity select lut truth table dff registers 0: 3-bit lut11 in1 1: dff8 d 0: 3-bit lut11 in2 1: dff8 nrst/nset 0: 3-bit lut11 out 1: dff8 out 0: 3-bit lut11 in0 1: dff8 clk s0 s1 s0 s1 s0 s1 s0 s1
SLG46536_ds_105 page 51 of 164 SLG46536 figure 20. 3-bit lut12 or dff9 with rst/set figure 21. 3-bit lut13 or dff10 with rst/set dff9 clk d 8-bits nvm 1-bit nvm 3-bit lut12 out in1 in2 in0 nrst/nset from connection matrix output <5> from connection matrix output <4> from connection matrix output <3> reg <1383:1376> reg <1366> to connection matrix input <41> q/nq reg <1383> dff or latch select reg <1382> output select (q or nq) reg <1381> dff nrst or nset select reg <1380> dff initial polarity select lut truth tab l e dff registers 0: 3-bit lut12 in1 1: dff9 d 0: 3-bit lut12 in2 1: dff9 nrst/nset 0: 3-bit lut12 out 1: dff9 out 0: 3-bit lut12 in0 1: dff9 clk s0 s1 s0 s1 s0 s1 s0 s1 dff10 clk d to connection matrix input <42> 8-bits nvm from connection matrix output <8> 1-bit nvm 3-bit lut13 out in1 in2 in0 nrst/nset from connection matrix output <7> from connection matrix output <6> reg <1391:1384> reg <1365> q/nq reg <1391> dff or latch select reg <1390> output select (q or nq) reg <1389> dff nrst or nset select reg <1388> dff initial polarity select lut truth table dff registers 0: 3-bit lut13 in1 1: dff10 d 0: 3-bit lut13 in2 1: dff10 nrst/nset 0: 3-bit lut13 out 1: dff10 out 0: 3-bit lut13 in0 1: dff10 clk s0 s1 s0 s1 s0 s1 s0 s1
SLG46536_ds_105 page 52 of 164 SLG46536 figure 22. 3-bit lut14 or dff11with rst/set figure 23. 3-bit lut15 or dff12 with rst/set dff11 clk d to connection matrix input <43> 8-bits nvm from connection matrix output <11> 1-bit nvm 3-bit lut14 out in1 in2 in0 nrst/nset from connection matrix output <10> from connection matrix output <9> reg <1399:1392> reg <1364> q/nq reg <1399> dff or latch select reg <1398> output select (q or nq) reg <1397> dff nrst or nset select reg <1396> dff initial polarity select lut truth table dff registers 0: 3-bit lut14 in1 1: dff11 d 0: 3-bit lut14 in2 1: dff11 nrst/nset 0: 3-bit lut14 out 1: dff11 out 0: 3-bit lut14 in0 1: dff11 clk s0 s1 s0 s1 s0 s1 s0 s1 dff12 clk d to connection matrix input <44> 8-bits nvm from connection matrix output <14> 1-bit nvm 3-bit lut15 out in1 in2 in0 nrst/nset from connection matrix output <13> from connection matrix output <12> reg <1407:1400> reg <1363> q/nq reg <1407> dff or latch select reg <1406> output select (q or nq) reg <1405> dff nrst or nset select reg <1404> dff initial polarity select lut truth table dff registers 0: 3-bit lut15 in1 1: dff12 d 0: 3-bit lut15 in2 1: dff12 nrst/nset 0: 3-bit lut15 out 1: dff12 out 0: 3-bit lut15 in0 1: dff12 clk s0 s1 s0 s1 s0 s1 s0 s1
SLG46536_ds_105 page 53 of 164 SLG46536 figure 24. 3-bit lut16 or dff13 with rst/set figure 25. 3-bit lut17 or dff14 with rst/set dff13 clk d 8-bits nvm 1-bit nvm 3-bit lut16 out in1 in2 in0 nrst/nset from connection matrix output <17> from connection matrix output <16> from connection matrix output <15> reg <1415:1408> reg <1362> to connection matrix input <45> q/nq reg <1415> dff or latch select reg <1414> output select (q or nq) reg <1413> dff nrst or nset select reg <1412> dff initial polarity select lut truth tab l e dff registers 0: 3-bit lut16 in1 1: dff13 d 0: 3-bit lut16 in2 1: dff13 nrst/nset 0: 3-bit lut16 out 1: dff13 out 0: 3-bit lut16 in0 1: dff13 clk s0 s1 s0 s1 s0 s1 s0 s1 dff14 clk d to connection matrix input <46> 8-bits nvm from connection matrix output <20> 1-bit nvm 3-bit lut17 out in1 in2 in0 nrst/nset from connection matrix output <19> from connection matrix output <18> reg <1423:1416> reg <1361> q/nq reg <1423> dff or latch select reg <1422> output select (q or nq) reg <1421> dff nrst or nset select reg <1420> dff initial polarity select lut truth table dff registers 0: 3-bit lut17 in1 1: dff14 d 0: 3-bit lut17 in2 1: dff14 nrst/nset 0: 3-bit lut17 out 1: dff14 out 0: 3-bit lut17 in0 1: dff14 clk s0 s1 s0 s1 s0 s1 s0 s1
SLG46536_ds_105 page 54 of 164 SLG46536 9.2.1 3-bit lut or d flip flop macrocells used as 3-bit luts table 36. 3-bit lut0 truth table in2 in1 in0 out 0 0 0 reg <1216> lsb 0 0 1 reg <1217> 0 1 0 reg <1218> 0 1 1 reg <1219> 1 0 0 reg <1220> 1 0 1 reg <1221> 1 1 0 reg <1222> 1 1 1 reg <1223> msb table 37. 3-bit lut1 truth table in2 in1 in0 out 0 0 0 reg <1224> lsb 0 0 1 reg <1225> 0 1 0 reg <1226> 0 1 1 reg <1227> 1 0 0 reg <1228> 1 0 1 reg <1229> 1 1 0 reg <1230> 1 1 1 reg <1231> msb table 38. 3-bit lut2 truth table in2 in1 in0 out 0 0 0 reg <1232> lsb 0 0 1 reg <1233> 0 1 0 reg <1234> 0 1 1 reg <1235> 1 0 0 reg <1236> 1 0 1 reg <1237> 1 1 0 reg <1238> 1 1 1 reg <1239> msb table 39. 3-bit lut3 truth table in2 in1 in0 out 0 0 0 reg <1240> lsb 0 0 1 reg <1241> 0 1 0 reg <1242> 0 1 1 reg <1243> 1 0 0 reg <1244> 1 0 1 reg <1245> 1 1 0 reg <1246> 1 1 1 reg <1247> msb table 40. 3-bit lut4 truth table in2 in1 in0 out 0 0 0 reg <1248> lsb 0 0 1 reg <1249> 0 1 0 reg <1250> 0 1 1 reg <1251> 1 0 0 reg <1252> 1 0 1 reg <1253> 1 1 0 reg <1254> 1 1 1 reg <1255> msb table 41. 3-bit lut11 truth table in2 in1 in0 out 0 0 0 reg <1368> lsb 0 0 1 reg <1369> 0 1 0 reg <1370> 0 1 1 reg <1371> 1 0 0 reg <1372> 1 0 1 reg <1373> 1 1 0 reg <1374> 1 1 1 reg <1375> msb table 42. 3-bit l ut12 truth table in2 in1 in0 out 0 0 0 reg <1376> lsb 0 0 1 reg <1377> 0 1 0 reg <1378> 0 1 1 reg <1379> 1 0 0 reg <1380> 1 0 1 reg <1381> 1 1 0 reg <1382> 1 1 1 reg <1383> msb table 43. 3-bit l ut13 truth table in2 in1 in0 out 0 0 0 reg <1384> lsb 0 0 1 reg <1385> 0 1 0 reg <1386> 0 1 1 reg <1387> 1 0 0 reg <1388> 1 0 1 reg <1389> 1 1 0 reg <1390> 1 1 1 reg <1391> msb
SLG46536_ds_105 page 55 of 164 SLG46536 each macrocell, when programmed for a lut function, uses a 8-bi t register to define their output function: 3-bit lut0 is defined by reg<1223:1216> 3-bit lut1 is defined by reg<1231:1324> 3-bit lut2 is defined by reg<1239:1232> 3-bit lut3 is defined by reg<1247:1240> 3-bit lut4 is defined by reg<1255:1248> 3-bit lut11 is defined by reg<1375:1368> 3-bit lut12 is defined by reg<1383:1376> 3-bit lut13 is defined by reg<1391:1384> 3-bit lut14 is defined by reg<1399:1392> 3-bit lut15 is defined by reg<1407:1400> 3-bit lut16 is defined by reg<1415:1408> 3-bit lut17 is defined by reg<1423:1416> table 44. 3-bit lut14 truth table in2 in1 in0 out 0 0 0 reg <1392> lsb 0 0 1 reg <1393> 0 1 0 reg <1394> 0 1 1 reg <1395> 1 0 0 reg <1396> 1 0 1 reg <1397> 1 1 0 reg <1398> 1 1 1 reg <1399> msb table 45. 3-bit lut15 truth table in2 in1 in0 out 0 0 0 reg <1400> lsb 0 0 1 reg <1401> 0 1 0 reg <1402> 0 1 1 reg <1403> 1 0 0 reg <1404> 1 0 1 reg <1405> 1 1 0 reg <1406> 1 1 1 reg <1407> msb table 46. 3-bit l ut16 truth table in2 in1 in0 out 0 0 0 reg <1408> lsb 0 0 1 reg <1409> 0 1 0 reg <1410> 0 1 1 reg <1411> 1 0 0 reg <1412> 1 0 1 reg <1413> 1 1 0 reg <1414> 1 1 1 reg <1415> msb table 47. 3-bit l ut17 truth table in2 in1 in0 out 0 0 0 reg <1416> lsb 0 0 1 reg <1417> 0 1 0 reg <1418> 0 1 1 reg <1419> 1 0 0 reg <1420> 1 0 1 reg <1421> 1 1 0 reg <1422> 1 1 1 reg <1423> msb
SLG46536_ds_105 page 56 of 164 SLG46536 the table below shows the regist er bits for the standard digita l logic devices (and, nand, or , nor, xor, xnor) that can be created within each of the s ix 3-bit lut logic cells. 9.2.2 3-bit lut or d flip flop macrocells used as d flip flop register settings table 48. 3-bit lut stand ard digital functions function msb lsb and-3 10000000 nand-3 01111111 or-3 11111110 nor-3 00000001 xor-3 10010110 xnor-3 01101001 table 49. dff3 register settings signal function register bit address register definition lut3_0 or dff3 select reg<1187> 0: lut3_0 1: dff3 dff3 initial polarity select reg<1220> 0: low 1: high dff3 nrst/nset select reg<1221> 1: nset from matrix out 0: nrst from matrix out dff3 output select reg<1222> 0: q output 1: nq output dff3 or latch select reg<1223> 0: dff function 1: latch function table 50. dff4 register settings signal function register bit address register definition lut3_1 or dff4 select reg<1186> 0: lut3_1 1: dff4 dff4 initial polarity select reg<1128> 0: low 1: high dff4 nrst/nset select reg<1129> 1: nset from matrix out 0: nrst from matrix out dff4 output select reg<1130> 0: q output 1: nq output dff4 or latch select reg<1131> 0: dff function 1: latch function
SLG46536_ds_105 page 57 of 164 SLG46536 table 51. dff5 register settings signal function register bit address register definition lut3_2 or dff5 select reg<1185> 0: lut3_2 1: dff5 dff5 initial polarity select reg<1236> 0: low 1: high dff5 nrst/nset select reg<1237> 1: nset from matrix out 0: nrst from matrix out dff5 output select reg<1238> 0: q output 1: nq output dff5 or latch select reg<1239> 0: dff function 1: latch function table 52. dff6 register settings signal function register bit address register definition lut3_3 or dff6 select reg<1184> 0: lut3_3 1: dff6 dff6 initial polarity select reg<1244> 0: low 1: high dff6 nrst/nset select reg<1245> 1: nset from matrix out 0: nrst from matrix out dff6 output select reg<1246> 0: q output 1: nq output dff6 or latch select reg<1247> 0: dff function 1: latch function table 53. dff7 register settings signal function register bit address register definition lut3_4 or dff7 select reg<1199> 0: lut3_4 1: dff7 dff7 initial polarity select reg<1252> 0: low 1: high dff7 nrst/nset select reg<1253> 1: nset from matrix out 0: nrst from matrix out dff7 output select reg<1254> 0: q output 1: nq output dff7 or latch select reg<1255> 0: dff function 1: latch function
SLG46536_ds_105 page 58 of 164 SLG46536 table 54. dff8 register settings signal function register bit address register definition lut3_11 or dff8 select reg<1367> 0: lut3_2 1: dff8 dff8 initial polarity select reg<1372> 0: low 1: high dff8 nrst/nset select reg<1373> 1: nset from matrix out 0: nrst from matrix out dff8 output select reg<1374> 0: q output 1: nq output dff8 or latch select reg<1375> 0: dff function 1: latch function table 55. dff9 register settings signal function register bit address register definition lut3_12 or dff9 select reg<1366> 0: lut3_12 1: dff9 dff9 initial polarity select reg<1380> 0: low 1: high dff9 nrst/nset select reg<1381> 1: nset from matrix out 0: nrst from matrix out dff9 output select reg<1382> 0: q output 1: nq output dff9 or latch select reg<1383> 0: dff function 1: latch function table 56. dff10 register settings signal function register bit address register definition lut3_13 or dff10 select reg<1365> 0: lut3_13 1: dff10 dff10 initial polarity select reg<1388> 0: low 1: high dff10 nrst/nset select reg<1389> 1: nset from matrix out 0: nrst from matrix out dff10 output select reg<1390> 0: q output 1: nq output dff10 or latch select reg<1391> 0: dff function 1: latch function
SLG46536_ds_105 page 59 of 164 SLG46536 table 57. dff11 register settings signal function register bit address register definition lut3_14 or dff11 select reg<1364> 0: lut3_2 1: dff11 dff11 initial polarity select reg<1396> 0: low 1: high dff11 nrst/nset select reg<1397> 1: nset from matrix out 0: nrst from matrix out dff11 output select reg<1398> 0: q output 1: nq output dff11 or latch select reg<1399> 0: dff function 1: latch function table 58. dff12 register settings signal function register bit address register definition lut3_15 or dff12 select reg<1363> 0: lut3_3 1: dff12 dff12 initial polarity select reg<1404> 0: low 1: high dff12 nrst/nset select reg<1405> 1: nset from matrix out 0: nrst from matrix out dff12 output select reg<1406> 0: q output 1: nq output dff12 or latch select reg<1407> 0: dff function 1: latch function table 59. dff13 register settings signal function register bit address register definition lut3_16 or dff13 select reg<1362> 0: lut3_4 1: dff13 dff13 initial polarity select reg<1412> 0: low 1: high dff13 nrst/nset select reg<1413> 1: nset from matrix out 0: nrst from matrix out dff13 output select reg<1414> 0: q output 1: nq output dff13 or latch select reg<1415> 0: dff function 1: latch function
SLG46536_ds_105 page 60 of 164 SLG46536 table 60. dff14 register settings signal function register bit address register definition lut3_17 or dff14 select reg<1361> 0: lut3_17 1: dff14 dff14 initial polarity select reg<1420> 0: low 1: high dff14 nrst/nset select reg<1421> 1: nset from matrix out 0: nrst from matrix out dff14 output select reg<1422> 0: q output 1: nq output dff14 or latch select reg<1423> 0: dff function 1: latch function
SLG46536_ds_105 page 61 of 164 SLG46536 9.3 initial polarity operations figure 26. dff polarity operations with nreset
SLG46536_ds_105 page 62 of 164 SLG46536 figure 27. dff polarity operations with nset
SLG46536_ds_105 page 63 of 164 SLG46536 9.4 3-bit lut or pipe delay macrocell there is one macrocell that can serve as either a 3-bit lut or as a pipe delay. when used to implement lut functions, the 3-bit lut take in thr ee input signals from the connection matrix and produces a sing le output, which goes back in to the connection matrix. when used as a pipe delay, there are three inputs signals from the matrix, input (in), clock (c lk) and reset (nrst). the pipe delay cell is built from 16 d flip-flop logic cells that provid e the three output opt ions, two of which ar e user selectable. t he dff cells are tied in series where the output (q) of each delay cel l goes to the next dff cell. the first delay option is fixed at the output of the first flip-flop stage. the other two outputs (out0 and o ut1) provide user selectable options for 1 C 16 stages of delay there are delay output points for each set of the out0 and out1 outputs to a 16-input mux that is controlled by reg <1259:1256 > for out0 and reg <1263:1260> for out1. the 16-input mux is used to select the amount of delay. the overall time of the delay is based on the clock used in the SLG46536 design. each dff cell has a time delay of the inverse of the clock time (either extern al clock or the r c oscillator w ithin the SLG46536). th e sum of the number of dff cells used wi ll be the total time delay of the pipe delay logic cell. note: clk is rising edge triggered. figure 28. 3-bit lut10 or pipe delay 3-bit lut10 out in1 in0 reg <1263:1256> from connection matrix output <98> from connection matrix output <99> in2 from connection matrix output <100> 16 flip-flops nrst in clk from connection matrix output <98> from connection matrix output <99> from connection matrix output <100> reg <1263:1260> reg <1259:1256> to connection matrix input<26> to connection matrix input <25> out1 out0 reg <1271> to connection matrix input <24> 1 pipe out reg <1270> s0 s1 s0 s1 lut truth ta bl e
SLG46536_ds_105 page 64 of 164 SLG46536 9.4.1 3-bit lut or pipe delay macrocells used as 3-bit luts each macrocell, when programmed for a lut function, uses a 8-bi t register to define their output function: 3-bit lut10 is defined by reg<1263:1256> 9.4.2 3-bit lut or pipe delay macrocells used as pipe delay r egister settings table 62. pipe delay register settings signal function register bit address register definition lut3_10 or pipe delay output select reg<1270> 0: lut3_10 1: 1 pipe delay output out0 select reg<1259:1256> out1 select reg<1263:1260> pipe delay out1 polarity select bit reg<1271> 0: non-inverted 1: inverted table 61. 3-bit lut10 truth table in2 in1 in0 out 0 0 0 reg <1256> lsb 0 0 1 reg <1257> 0 1 0 reg <1258> 0 1 1 reg <1259> 1 0 0 reg <1260> 1 0 1 reg <1261> 1 1 0 reg <1262> 1 1 1 reg <1263> msb
SLG46536_ds_105 page 65 of 164 SLG46536 9.5 3-bit lut or 8-bit counter / delay macrocells there are five macrocells that c an serve as either 3-bit luts o r as counter / delays. when used to implement lut function, the 3-bit lut takes in three input signals from the connection matr ix and produces a single output, which goes back into the conne c- tion matrix. when used to implem ent 8-bit counter / delay funct ion, two of the three input signal s from the connection matrix go to the external clock (ext_clk) and reset (dly_in/cnt_reset) fo r the counter/delay, with the output going back to the connecti on matrix. these macrocells can also opera te in a one-shot mode, which wil l generate an output puls e of user-defined width. these macrocells can also operate in a frequency detection or e dge detection mode. for timing diagrams refer to section 9.7 cnt/dly/fsm timing diagrams . two of the five macrocells can have their active count value re ad via i 2 c (cnt4 and cnt6). see section 18.5.1.2 reading counter data via i2c for further details. 9.5.1 3-bit lut or 8- bi t cnt/dly block diagrams figure 29. 3-bit lut5 or cnt/dly2 cnt/dly2 out clk dly_in/cnt_reset 3-bit lut5 out in0 in1 8-bits nvm 1-bit nvm in2 reg <1543:1536> reg <1198> from connection matrix output <83> from connection matrix output <84> to connection matrix input <17> from connection matrix output <85> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut5 in1 1: cnt/dly2 clk 0: 3-bit lut5 out 1: cnt/dly2 out 0: 3-bit lut5 in0 1: cnt/dly2 rst
SLG46536_ds_105 page 66 of 164 SLG46536 figure 30. 3-bit lut6 or cnt/dly3 figure 31. 3-bit lut7 or cnt/dly4 cnt/dly3 out clk dly_in/cnt_reset 3-bit lut6 out in0 in1 8-bits nvm 1-bit nvm in2 reg <1551:1554> reg <1197> from connection matrix output <86> from connection matrix output <87> to connection matrix input <18> from connection matrix output <88> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut6 in1 1: cnt/dly3 clk 0: 3-bit lut6 out 1: cnt/dly3 out 0: 3-bit lut6 in0 1: cnt/dly3 rst cnt/dly4 out clk dly_in/cnt_reset 3-bit lut7 out in0 in1 8-bits nvm 1-bit nvm in2 reg <1559:1592> reg <1196> from connection matrix output <89> from connection matrix output <90> to connection matrix input <19> from connection matrix output <91> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut7 in1 1: cnt/dly4 clk 0: 3-bit lut7 out 1: cnt/dly4 out 0: 3-bit lut7 in0 1: cnt/dly4 rst
SLG46536_ds_105 page 67 of 164 SLG46536 figure 32. 3-bit lut8 or cnt/dly5 figure 33. 3-bit lut9 or cnt/dly6 cnt/dly5 out clk dly_in/cnt_reset 3-bit lut8 out in0 in1 8-bits nvm 1-bit nvm in2 reg <1567:1560> reg <1195> from connection matrix output <92> from connection matrix output <93> to connection matrix input <20> from connection matrix output <94> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut8 in1 1: cnt/dly5 clk 0: 3-bit lut8 out 1: cnt/dly5 out 0: 3-bit lut8 in0 1: cnt/dly5 rst cnt/dly6 out clk dly_in/cnt_reset 3-bit lut9 out in0 in1 8-bits nvm 1-bit nvm in2 reg <1575:1568> reg <1194> from connection matrix output <95> from connection matrix output <96> to connection matrix input <21> from connection matrix output <97> lut truth ta b l e cnt data s0 s1 s0 s1 s0 s1 0: 3-bit lut9 in1 1: cnt/dly6 clk 0: 3-bit lut9 out 1: cnt/dly6 out 0: 3-bit lut9 in0 1: cnt/dly6 rst
SLG46536_ds_105 page 68 of 164 SLG46536 9.5.2 3-bit lut or cnt/d lys used as 3-bit luts each macrocell, when programmed for a lut function, uses a 8-bi t register to define their output function: 3-bit lut5 is defined by reg<1543:1536> 3-bit lut6 is defined by reg<1551:1544> 3-bit lut7 is defined by reg<1559:1552> 3-bit lut8 is defined by reg<1567:1560> 3-bit lut9 is defined by reg<1575:1568> table 63. 3-bit lut5 truth table in2 in1 in0 out 0 0 0 reg <1536> lsb 0 0 1 reg <1537> 0 1 0 reg <1538> 0 1 1 reg <1539> 1 0 0 reg <1540> 1 0 1 reg <1541> 1 1 0 reg <1542> 1 1 1 reg <1543> msb table 64. 3-bit lut6 truth table in2 in1 in0 out 0 0 0 reg <1544> lsb 0 0 1 reg <1545> 0 1 0 reg <1546> 0 1 1 reg <1547> 1 0 0 reg <1548> 1 0 1 reg <1549> 1 1 0 reg <1550> 1 1 1 reg <1551> msb table 65. 3-bit lut7 truth table in2 in1 in0 out 0 0 0 reg <1552> lsb 0 0 1 reg <1553> 0 1 0 reg <1554> 0 1 1 reg <1555> 1 0 0 reg <1556> 1 0 1 reg <1557> 1 1 0 reg <1558> 1 1 1 reg <1559> msb table 66. 3-bit lut8 truth table in2 in1 in0 out 0 0 0 reg <1560> lsb 0 0 1 reg <1561> 0 1 0 reg <1562> 0 1 1 reg <1563> 1 0 0 reg <1564> 1 0 1 reg <1565> 1 1 0 reg <1566> 1 1 1 reg <1567> msb table 67. 3-bit lut9 truth table in2 in1 in0 out 0 0 0 reg <1568> lsb 0 0 1 reg <1569> 0 1 0 reg <1570> 0 1 1 reg <1571> 1 0 0 reg <1572> 1 0 1 reg <1573> 1 1 0 reg <1574> 1 1 1 reg <1575> msb
SLG46536_ds_105 page 69 of 164 SLG46536 9.5.3 3-bit lut or 8-bit count er / delay macrocells used as 8 -bit counter / delay register settings table 68. cnt/dly2 register settings signal function register bit address register d efinition lut3_5 or counter2 select reg<1198> 0: lut3_5 1: counter2 delay2 mode select or asynchronous counter reset reg<1273:1272> 00: on both falli ng and rising edges (for delay & counter reset) 01: on falling edge only (fo r delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or rising edges / counter high l evel reset counter/delay2 clock source select reg<1276:1274> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter1 overflow counter/delay2 output selection for counter mode reg<1277> 0: default output 1: edge dete ctor output counter/delay2 mode selection reg<1279:1278> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay2 control data reg<1543:1536> 1 C 255 table 69. cnt/dly3 register settings signal function register bit address register d efinition lut3_6 or counter3 select reg<1197> 0: lut3_6 1: counter3 delay3 mode select or asynchronous counter reset reg<1281:1280> 00: on both falli ng and rising edges (for delay & counter reset) 01: on falling edge only (fo r delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or rising edges / counter high l evel reset counter/delay3 clock source select reg<1284:1282> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter2 overflow counter/delay3 output selection for counter mode reg<1285> 0: default output 1: edge dete ctor output counter/delay2 mode selection reg<1287:1286> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay3 control data reg<1551:1544> 1 C 255
SLG46536_ds_105 page 70 of 164 SLG46536 table 70. cnt/dly4 register settings signal function register bit address register definition lut3_7 or counter4 select reg<1196> 0: lut3_7 1: counter4 delay4 mode select or asynchronous counter reset reg<1289:1288> 00: on both falling and risi ng edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only ( for delay & counter reset) 11: no delay on either falling or rising edges / counter high l evel reset counter/delay4 clock source select reg<1292:1290> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter3 overflow counter/delay4 output selection for counter mode reg<1293> 0: default output 1: edge dete ctor output counter/delay4 mode selection reg<1295:1294> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay4 control data reg<1559:1552> 1 C 255 table 71. cnt/dly5 register settings signal function register bit address register definition lut3_8 or counter5 select reg<1195> 0: lut3_8 1: counter5 delay5 mode select or asynchronous counter reset reg<1297:1296> 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or r ising edges / counter high l evel reset counter/delay5 clock source select reg<1300:1298> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter4 overflow counter/delay5 output selection for counter mode reg<1301> 0: default output 1: edge detector output counter/delay5 mode selection reg<1303:1302> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay5 control data reg<1567:1560> 1 C 255
SLG46536_ds_105 page 71 of 164 SLG46536 table 72. cnt/dly6 register settings signal function register bit address register definition lut3_9 or counter5 select reg<1194> 0: lut3_9 1: counter6 delay6 mode select or asynchronous counter reset reg<1305:1304> 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or r ising edges / counter high l evel reset counter/delay6 clock source select reg<1308:1306> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter5 overflow counter/delay6 output selection for counter mode reg<1309> 0: default output 1: edge detector output counter/delay6 mode selection reg<1311:1310> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay6 control data reg<1575:1568> 1 C 255
SLG46536_ds_105 page 72 of 164 SLG46536 9.6 4-bit lut or 16-bit counter / delay macrocells there are two macrocells that can serve as either 4-bit luts or as 16-bit counter / delays. when used to implement lut functio n, the 4-bit lut takes in four input signals from the connection m atrix and produces a single output, which goes back into the connection matrix. when used to implement 16-bit counter / dela y function, four input signals fr om the connection matrix go to the external clock (ext_clk), reset (dly_in/cnt_reset), keep an d up for the counter/delay, wit h the output going back to the connection matrix. these two macrocells have an optional finite state machine (fsm ) function. there are two ma trix inputs for up and keep to support fsm functionality. any counter within green pak is coun ting down by default. in fsm mode (cnt/dly0 and cnt/dly1) it is possible to reverse counting by applying high level to up input. also, there is a possibility to pause counting by apply ing high level to keep input, after the level goes low, the counter will proceed counting. these macrocells can also opera te in a one-shot mode, which wil l generate an output puls e of user-defined width. these macrocells can also opera te in a frequency detection. delay time and output period c an be calculated us ing the follow ing formulas: ? delay time: [(counter data + 2) / clk in put frequency C offset *]; ? output period: [(count er data + 1) / clk i nput frequency C off set*]; one shot pulse width can be calculated us ing formula: ? pulse width = [(counter data + 2) / clk input frequency C offs et*]; *offset is the asynchronous time offset between the input signa l and the first clock pulse. for timing diagrams refer to section 9.7 cnt/dly/fsm timing diagrams both of these macrocells can hav e their active count value read via i 2 c. see section 18.5.1.2 reading counter data via i2c for further details
SLG46536_ds_105 page 73 of 164 SLG46536 9.6.1 4-bit lut or 16-bi t cnt/dly block diagram figure 34. 4-bit lut0 or cnt/dly0 cnt/dly0 out clk dly_in/cnt_reset 4-bit lut0 out in0 in1 16-bits nvm 1-bit nvm in2 in3 reg <1591:1576> reg <1193> from connection matrix output <101> from connection matrix output <104> from connection matrix output <102> to connection matrix input <22> fsm up keep from connection matrix output <103> lut truth table cnt data 0: 4-bit lut0 in1 1: cnt/dly0 clk 0: 4-bit lut0 out 1: cnt/dly0 out 0: 4-bit lut0 in0 1: cnt/dly0 rst 0: 4-bit lut0 in2 1: fsm up 0: 4-bit lut0 in3 1: fsm keep s0 s1 s0 s1 s0 s1 s0 s1 s0 s1
SLG46536_ds_105 page 74 of 164 SLG46536 figure 35. 4-bit lut1 or cnt/dly1 cnt/dly1 out clk dly_in/cnt_reset 4-bit lut1 out in0 in1 16-bits nvm 1-bit nvm in2 in3 reg <1607:1592> reg <1192> from connection matrix output <105> from connection matrix output <108> from connection matrix output <106> to connection matrix input <23> fsm up keep from connection matrix output <107> lut truth table cnt data 0: 4-bit lut1 in1 1: cnt/dly1 clk 0: 4-bit lut1 out 1: cnt/dly1 out 0: 4-bit lut1 in0 1: cnt/dly1 rst 0: 4-bit lut1 in2 1: fsm up 0: 4-bit lut1 in3 1: fsm keep s0 s1 s0 s1 s0 s1 s0 s1 s0 s1
SLG46536_ds_105 page 75 of 164 SLG46536 9.6.2 4-bit lut or 16-bit coun ter / delay macrocells used as 4-bit luts each macrocell, when programmed for a lut function, uses a 16-b it register to define their output function: 4-bit lut0 is defined by reg<1591:1576> 4-bit lut1 is defined by reg<1607:1592> table 75. 4-bit lut stand ard digital functions function msb lsb and-4 1000000000000000 nand-40111111111111111 or-4 1111111111111110 nor-4 0000000000000001 xor-4 0110100110010110 xnor-41001011001101001 table 73. 4-bit lut0 truth table. in3 in2 in1 in0 out 0 0 0 0 reg <1576> lsb 0 0 0 1 reg <1577> 0 0 1 0 reg <1578> 0 0 1 1 reg <1579> 0 1 0 0 reg <1580> 0 1 0 1 reg <1581> 0 1 1 0 reg <1582> 0 1 1 1 reg <1583> 1 0 0 0 reg <1584> 1 0 0 1 reg <1585> 1 0 1 0 reg <1586> 1 0 1 1 reg <1587> 1 1 0 0 reg <1588> 1 1 0 1 reg <1589> 1 1 1 0 reg <1590> 1 1 1 1 reg <1591> msb table 74. 4-bit lut1 truth table. in3 in2 in1 in0 out 0 0 0 0 reg <1592> lsb 0 0 0 1 reg <1593> 0 0 1 0 reg <1594> 0 0 1 1 reg <1595> 0 1 0 0 reg <1596> 0 1 0 1 reg <1597> 0 1 1 0 reg <1598> 0 1 1 1 reg <1599> 1 0 0 0 reg <1600> 1 0 0 1 reg <1601> 1 0 1 0 reg <1602> 1 0 1 1 reg <1603> 1 1 0 0 reg <1604> 1 1 0 1 reg <1605> 1 1 1 0 reg <1606> 1 1 1 1 reg <1607> msb
SLG46536_ds_105 page 76 of 164 SLG46536 9.6.3 4-bit lut or 16-bit coun ter / delay macrocells used as 16-bit counter / delay register settings table 76. cnt/dly0 register settings signal function register bit address register d efinition lut4_0 or counter0 select reg<1193> 0: lut4_0 1: counter0 delay0 mode select or asynchronous counter reset reg<1313:1312> 00: on both falli ng and rising edges (for delay & counter reset) 01: on falling edge only (fo r delay & counter reset) 10: on rising edge only (fo r delay & counter reset) 11: no delay on either falling or rising edges / counter high l evel reset counter/delay0 clock source select reg<1316:1314> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter6 overflow c n t 0 / f s m 0 ' s q a r e set to data or reset to 0s selection reg<1317> 0: reset to 0s 1: set to control data counter/delay0 mode selection reg<1319:1318> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay0 control data reg<1591:1576> 1 - 16535 table 77. cnt/dly1 register settings signal function register bit address register definition lut4_1 or counter1 select reg<1192> 0: lut4_1 1: counter1 delay1 mode select or asynchronous counter reset reg<1321:1320> 00: on both falling and risin g edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / counter high l evel reset counter/delay1 clock source select reg<1324:1322> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter0 overflow c n t 0 / f s m 0 ' s q a r e set to data or reset to 0s selection reg<1325> 0: reset to 0s 1: set to control data counter/delay1 mode selection reg<1327:1326> 00: delay mode 01: one shot 10: freq. detect 11: counter mode counter/delay1 control data reg<1607:1592> 1 - 16535
SLG46536_ds_105 page 77 of 164 SLG46536 9.7 cnt/dly/fsm timing diagrams 9.7.1 delay mode (edge select: both, counter data: 3) cnt/dly 2...cnt/dly6 9.7.2 count mode (co unt data: 3), counter reset (rising edge detect) cnt/dly2...cnt/dly6 figure 36. delay mode timing diagram figure 37. counter mode timing diagram delay in rc osc: force power on (always running) delay output asynchronous delay variable asynchronous delay variable delay = period x (counter data + 1) + variable variable is from 0 to 1 clock period delay = period x (counter data + 1) + variable variable is from 0 to 1 clock period delay in rc osc: auto power on (powers up from delay in) delay output offset offset delay = offset + period x (counter data + 1) see offset in table 3 delay = offset + period x (counter data + 1) see offset in table 3 reset_in clk counter out count start in 0 clk after reset 4 clk period pulse
SLG46536_ds_105 page 78 of 164 SLG46536 9.7.3 one-shot mode cnt/dly0...cnt/dly6 this macrocell will generate a pulse whenever a selected edge i s detected on its input. register bits set the edge selection. the pulse width determines by counter data and clock selection prop erties. the output pulse polarity (non-inverted or inverted) is selected by register bit. see table 78. any incoming edges will be ignored during the pulse width gener ation. the following diagram shows one-shot functi on for non-inverted output. figure 38. one-shot function timing diagram one-shot/freq. det/delay in one-shot function rising edge detection one-shot function falling edge detection one-shot function both edge detection t t t t delay time delay time delay time delay time delay time delay time
SLG46536_ds_105 page 79 of 164 SLG46536 this macrocell generates a high level pulse with a set width (d efined by counter data) when dete cting the respective edge. it does not restart while pulse is high. 9.7.4 frequency detection mode cnt/dly0...cnt/dly6 rising edge: the output goes high if the time between two succe ssive edges is less than the delay. the output goes low if the second rising edge has not come a fter the last rising edge in s pecified time. falling edge: the output goes high if the time between two fall ing edges is less than the set time. the output goes low if the second falling edge has not come after the last falling edge in specified time. both edge: the output goes high if the time betwe en the rising and falling edges is less than the set time, which is equivalen t to the length of the pulse. the output goes low if after the last rising/falling edge and specified time, the second edge has not come. table 78. dly/cntx one-shot / freq. detect output polarity address signal function register bit definition i 2 c interface byte register bit read write a6 reg<1329> select the polarity of dly/cnt6's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1330> select the polarity of dly/cnt5's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1331> select the polarity of dly/cnt4's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1332> select the polarity of dly/cnt3's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1333> select the polarity of dly/cnt2's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1334> select the polarity of dly/cnt1's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1335> select the polarity of dly/cnt0's one shot / freq. detect output 0: default output 1: inverted output valid valid
SLG46536_ds_105 page 80 of 164 SLG46536 figure 39. frequency detection mode timing diagram one-shot/freq. det/delay in frequency detector function rising edge detection frequency detector function falling edge detection frequency detector function both edge detection t t t t delay time delay time delay time delay time delay time delay time
SLG46536_ds_105 page 81 of 164 SLG46536 9.7.5 edge detection mode cnt/dly2...cnt/dly6 the macrocell generates high level short pulse when detecting t he respective edge. see table 4. expected delays and widths (typical). figure 40. edge detection mode timing diagram one-shot/freq. det/delay in edge detector function rising edge detection edge detector function falling edge detection edge detector function both edge detection t t t t delay time delay time delay time delay time delay time
SLG46536_ds_105 page 82 of 164 SLG46536 9.7.6 delay mode cnt/dly0...cnt/dly6 the macrocell shifts the respective edge to a set time and rest arts by appropriate edge. it works as a filter if the input sig nal is shorter than the delay time. figure 41. delay mode timing diagram one-shot/freq. det/delay in delay function rising edge detection delay function falling edge detection delay function both edge detection t t t t delay time delay time delay time delay time delay time delay time
SLG46536_ds_105 page 83 of 164 SLG46536 9.7.7 cnt/fsm mode c nt/dly0, cnt/dly1 figure 42. cnt/fsm timing diagra m (reset rising edge mode, oscil lator is forced on, up=0) for counter data = 3 figure 43. cnt/fsm timing diagram (set rising edge mode, oscilla tor is forced on, up=0) for counter data = 3 reset in clk 313210 q count end 321 0 0 keep 2 32 10 note: q = current counter value set in clk 312103 q count end 210 3 3 keep 2 21 03 note: q = current counter value
SLG46536_ds_105 page 84 of 164 SLG46536 figure 44. cnt/fsm timing diagra m (reset rising edge mode, osci llator is forced on, up=1 ) for counter data = 3 figure 45. cnt/fsm timing diagra m (set rising edge mode, oscill ator is forced on, up=1) for counter data = 3 reseti n clk 3 5 1234 q count end 567 8 0 keep 4 9 16381 16382 3 45 note: q = current counter value 16383 set in clk 3 5 4567 q count end 8910 11 3 keep 4 12 16381 16382 16383 3 45 note: q = current counter value
SLG46536_ds_105 page 85 of 164 SLG46536 9.7.8 difference in counter val ue for counter, delay, one-sho t and frequency detect modes there is a difference in counter value for counter and delay/on e-shot/frequency detect modes. the counter value is shifted for two rising edges of the clock signal in delay/one-shot/frequenc y detect modes compared to counter mode. see figure 46. 9.8 2-bit lut or progr ammable pattern generator the SLG46536 has one combination function macrocell that can se rve as a logic or timing function. this macrocell can serve as a look up table (lut), or progra mmable pattern generator (pgen) . when used to implement lut functions, the 2-bit lut takes in tw o input signals from the connection matrix and produce a single output, which goes back into the connection matrix. when used a s a lut to implement combinatorial logic functions, the outputs of the luts can be configured to any user defined function, inc luding the following standard digital logic devices (and, nand, or, nor, xor, xnor). the user can also define the combinatorial relationship between inputs and outputs to be any selectable function. when operating as a programmable pattern generator, the output of the macrocell with clock out a sequence of two to sixteen bits that are user selectable in their bit values, and user sel ectable in the number of bits (u p to sixteen) that are output b efore the pattern repeats. see figure figure 48. figure 46. counter value, counter data = 3 one-shot/freq.set/delay in clk cnt out delay data one-shot out one-shot data dly out cnt data 0 3 2 1 0 3 2 3 3 3 2 1 3 3 3 3 3 2 1 3 3
SLG46536_ds_105 page 86 of 164 SLG46536 figure 47. 2-bit lut2 or pgen figure 48. pgen timing diagram pgen out clk nrst 2-bit lut3 out to connection matrix input <11> from connection matrix output <66> reg <1211:1208> reg <1188> from connection matrix output <67> in0 in1 reg <1623:1608> lut truth table pattern data pgen size 0: 2-bit lut3 out 1: pgen out s0 s1 vdd out d15 clk d0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 d14 d0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 t t t t nrst
SLG46536_ds_105 page 87 of 164 SLG46536 9.9 wake and sleep controller (ws) the SLG46536 has a wake and sleep function for all acmps. the m acrocell cnt/dly0 can be reconfigured for this purpose reg<1319:1318>=11 and reg<1495>=1. the ws serves for power savi ng, it allows to switch on and off selected acmps on selected bit of 16-bit counter. to use any acmp under ws controller the following settings must be done: ? acmp power up input f rom matrix = 1 (for each acmp separately) ; ? cnt/dly0 must be set to wake an d sleep controller function (fo r all acmps); ? register ws => enable (for each acmp separately); ? cnt/dly0 set/reset inpu t = 0 (for all acmps); ? in case of using osc1 (25 mhz), osc0 must be set to force powe r on. as the osc any oscillator with any pre divider can be used. the user can select a period of time while the acmps are sleeping in a range of 1 - 65535 clock cycles. before they are sent to s leep their outputs are latched so the acmps remain their state (high or low) while sleeping. ws controller has the following settings: ? wake and sleep output state (high/low) figure 49. ws controller osc ck_osc ws_pd 000:/1 001:/4 010:/12 011:/24 100:/64 cnt_end ws out ws_pd power control from connection matrix output<58> analog control block reg<1316:1314> ws_pd to w&s out state selection block ws clock freq. selection reg<1591:1576> ws ratio control data reg<1494> ws out state for osc off acmps_pdb ws out bg/regulator pdb ws time selection reg<1489> acmp0..2 out to connection matrix input <59:57> from connection matrix output <53:51> reg<1492:1490> acmp ws enable ws out latchs note: ws_pd is high at ws osc (25 khz/2mhz osc) power down ws controller cnt0 out to connection matrix input <22> ck cnt 3 3 3 acmps_pdb + - ws
SLG46536_ds_105 page 88 of 164 SLG46536 if osc is powered off (power down option is selected; power dow n input = 1) and wake and sleep output state = high, the acmp is continuously on if osc is powered off (power dow n option is selected; power dow n input = 1) and wake and sleep output state = low, the acmp is continuously off both cases ws func tion is turned off ? counter data (range: 1 - 65535) user can select wake and sleep ra tio of the acmp; counter data = sleep time, one clock = wake time ? q mode - defines the state of ws counter data when set/reset s ignal appears reset - when active signal appears, the ws counter will reset t o zero and high level signal on its output will turn the acmps on. when reset signal goes out, t he ws counter will go low and turn the acmps off until the c ounter counts up to the end set - when active signal appear s, the ws count er will stop and low level signal on it s output will turn the acmps off. when set signal goes out, the ws counter will go on counting and hig h level signal will turn the acmps on while counter is counting up to the end ? edge select defines the edge for q mode high level set/reset - switches mode set/reset when level is hi gh note: q mode operates only in ca se of "high le vel set/reset" ? wake time selection - time re quired for wake signal to turn th e acmps on normal wake time - when ws signal is high, it takes a bg time ( 100/550 s) to turn the acmps on they will stay on until ws signal is low again. wake time is one clock period. it shoul d be longer than bg turn on time and minimal required comparing time of the acmp short wake time - when ws signal is high, it takes a bg time (1 00/550 s) to turn the acmps on. they will stay on for 1 s and turn off regardless of ws si gnal. the ws signal width does not matter. ? keep - pauses counting while keep = 1 ? up - reverses counting if up = 1, cnt is counting up fr om user selected value to 65535 if up = 0, cnt is c ounting down from user selected value to 0
SLG46536_ds_105 page 89 of 164 SLG46536 9.9.1 ws register settings table 79. ws register settings signal function register bit address register definition counter/delay0 clock source select reg<1316:1314> 000: internal osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter6 overflow ws time selection reg<1489> 0: short wake time 1: normal wake time acmp0 wake & sleep function enable reg<1490> 0: disable 1: enable acmp1 wake & sleep function enable reg<1491> 0: disable 1: enable acmp2 wake & sleep function enable reg<1492> 0: disable 1: enable wake sleep output state when ws oscillator is power down if dly/cnt0 mode selection is "11" reg<1494> 0: low 1: high wake sleep ratio control mode selection if dly/cnt0 mode selection is "11" reg<1495> 0: default mode 1: wake sleep ratio control mode dly/cnt0 (16bits, <15:0> = <1591:1576>) control data reg<1591:1576> 1 - 65535
SLG46536_ds_105 page 90 of 164 SLG46536 10.0 analog comparators (acmp) there are three analog comparator (acmp) macrocells in the slg4 6536. in order for the acmp cells to be used in a greenpak design, the power up signals (acmpx_pdb) need to be active. by connecting to signals coming fr om the connection matrix, it is possible to have each acmp be always on, always off, or power c ycled based on a digital signal coming from the connection matrix. also, all acmps have wake and sleep function (ws), see section 9.9 wake and sleep controller (ws) . when acmp is powered down, output is low. pwr up = 1 => acmp is powered up. pwr up = 0 => acmp is powered down. during acmp power up, its output will remain low, and then beco mes valid 1.03 ms (max) after acmp power up signal goes high, see figure 51 . if vdd is greater or equal to 2.7 v, it is possible to decrea se turn-on time by setting the bg ok delay to 100 s, see figure 52 . the acmp cells have an input "low bandwidth" signal selection , which can be used to save power and reduce noise impact when lower bandwid th signals are being compared. t o ensure proper chip startup operation, it is recommended to enable the acmps with the por s ignal, and not t he vdd signal. note: regulator and charge pump set to automatic on/off . figure 50. maximum power on delay vs. vdd, bg = auto-delay. 120 140 160 180 200 220 240 1.71 1.8 2.5 2.7 3 3.3 3.6 4.2 4.5 5 5.5 power on delay (s) vdd (v) -40?c +25?c +85?c
SLG46536_ds_105 page 91 of 164 SLG46536 each of the acmp cells has a positive input signal that can be provided by a variety of external sources. there is also a sele ctable gain stage (1x, 0.5x, 0.33x, 0.2 5x) before connec tion to the an alog comparator. the gain divider is unbuffered and consists of 250 k (typ.) resistors, see table 80 . for gain divider accuracy refer to table 81 . in- voltage range: 0 - 1.2 v. can use vref selection vdd/4 and vdd/3 to maintain this input range. input bias current < 1 na (typ). each cell also has a hysteresis selection, to offer hysteresis of 0 mv, 25 mv, 50 mv or 200 mv. the 50 mv and 200 mv hysteresi s options can be used with internal voltage reference only, while 25 mv hysteresis option can be used with both internal and ext ernal voltage reference. the 50 mv and 200 mv hysteresis options are one way hysteresis. it means t hat the actual thresholds will be vref (high threshold) and vref - hysteresis (low threshold). th e acmp output will retain its previous value, if the input volt age is within threshold window (between vref and vref - hysteresis). p lease note: for the 25 mv hysteresis option threshold levels wi ll be vref + hysteresis/2 (high th reshold) and vref C hysteresis/2 (low threshold). note: any acmp powered on enables the bandgap internal circuit as well. an analog voltage will appear on vref even when the force bandgap option is set as disabled. table 80. gain divider input resistance gain x1 x0.5 x0.33 x0.25 input resistance 100 m 1 m 0.75 m 1 m table 81. gain di vider accuracy gain x0.5 x0.33 x0.25 accuracy 0.51% 0.34% 0.25% figure 51. maximum power on delay vs. vdd, bg = 550 s. 600 650 700 750 800 850 900 950 1000 1050 1100 1.71 1.8 2.5 2.7 3 3.3 3.6 4.2 4.5 5 5.5 power on delay (s) vdd (v) -40?c +25?c +85?c figure 52. maximum powe r on delay vs. vdd, bg = 100 s. 120 130 140 150 160 170 180 190 200 210 220 1.71 1.8 2.5 2.7 3 3.3 3.6 4.2 4.5 5 5.5 power on delay (s) vdd (v) -40?c +25?c +85?c
SLG46536_ds_105 page 92 of 164 SLG46536 for high input impedance when using the gain divider (x0.25, x0 .33, x0.5), it is possible to use the input buffer. however, th is will add some offset, see figure 53. it is not recommended to use acmp buffer when vdd < 2.5 v. note: when vdd < 1.8v voltage reference should not exceed 1100 mv. figure 53. typical buffer input voltage offset vs. voltage refer ence at t = (-40.... +85)c, buffer bandwidth = 1 khz, vhys = 0 mv, gain = 1. figure 54. typical input threshold variation (including vref var iation, acmp offset) vs. voltage reference at t = (-40.... +85)c, lmb mode - disable, v hys = 0 mv. -40 -30 -20 -10 0 10 20 30 40 50 250 600 850 1200 voffset (mv) voltage reference (mv) upper limit @ vdd2.7v lower limit @ vdd2.7v -25% -20% -15% -10% -5% 0% 5% 10% 15% 20% 50 150 250 350 450 550 650 750 850 950 1050 1150 input threshold variation (%) voltage reference (mv) upper limit lower limit
SLG46536_ds_105 page 93 of 164 SLG46536 10.1 acmp0 block diagram table 82. built-in hysteres is tolerance at t = 25c vhys (mv) vdd=(1.7-1.8) v vdd=(1.89-5.5) v vref = (50-500) mv vref = (550-1000) mv vref = (1050-1200) mv vref = (50-500) mv vref = (550-1000) mv vref = (1050-1200) mv min max min max min max min max min max min max 25 8.6 32.2 8.6 32.3 7.0 32. 5 8.5 32.3 8.5 32.3 7.8 34.0 50 44.8 56.5 43.9 56.7 42.7 56.4 44.2 56.8 43.6 57.3 43.1 56.0 200 192.8 207.9 194.0 208.0 192.7 205.4 192.0 208.6 193.0 209.5 190.8 207.7 figure 55. acmp0 block diagram 11010 11011 11100 11101 internal vref 110 100 0x1 pin4: acmp0(+) external vdd 1.71 v ~ 5.5 v external vdd 2.7 v ~ 5.5 v selectable gain reg <1630:1629> to acmp1, acmp2s mux input vref + - from connection matrix output <51> pdb lbw selection reg <1631> hysteresis selection reg <1175:1174> l/s to connection matrix input<57> reg <1628:1624> *pin4_aio_en; reg <1173>; reg <1172> *pin4_aio_en: if reg <1062:1061>=11 then 1, otherwise: 0 bg_ok latch 0 1 reg <1490> 11001- 00000 acmp0 wake & sleep function enable pin10: ext_vref pin10: ext_vref/2 pin5: acmp0(-) pin5: acmp0(-)/2
SLG46536_ds_105 page 94 of 164 SLG46536 10.2 acmp0 register settings table 83. acmp0 register settings signal function register bit address register definition acmp0 positive input source select reg<1172> 0: io4 1: vdd acmp0 analog buffer enable reg<1173> 0: disable analog buffer 1: enable analog buffer acmp0 hysteresis enable reg<1175:1174> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) (01: for both external & internal vref; 10 & 11: for only inter nal vref; external vref will not have 50mv & 200mv hysteresis.) acmp0 wake & sleep function enable reg<1490> 0: disable 1: enable acmp0 negative input voltage select reg<1628:1624> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: pin10: ext_vref 11011: pin5: acmp0- 11100: pin10: ext_vref/2 11101: pin5: acmp0-/2 acmp0 positive input divider reg<1630:1629> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp0 low bandwidth (max: 1 mhz) enable reg<1631> 0: off 1: on
SLG46536_ds_105 page 95 of 164 SLG46536 10.3 acmp1 block diagram figure 56. acmp1 block diagram 11011 11010 11100 11101 internal vref 11x 10x 0x1 pin8: acmp1(+) from acmp0's mux output pin4 external vdd 2.7 v ~ 5.5 v selectable gain reg <1638:1637> vref + - from connection matrix output <52> pdb lbw selection reg <1639> hysteresis selection avd = 1.8 v l/s to connection matrix input<58> reg <1636:1632> *pin8_aio_en; reg <1169>; reg <1168> *pin8_aio_en: if reg <1093:1092>=11 then 1, otherwise: 0 bg_ok latch 0 1 reg <1491> 11100- 00000 100 a current source acmp1 wake & sleep function enable en reg <1183> note: when 100 a current source is enabled input voltage on pi n 8 should not exceed 1.8 v pin10: acmp1(-) pin10: acmp1(-)/2 pin10: acmp1(-) pin10: acmp1(-)/2
SLG46536_ds_105 page 96 of 164 SLG46536 10.4 acmp1 register settings table 84. acmp1 register settings signal function register bit address register definition acmp1 100 a current source enable reg<1183> 0: disable 1: enable acmp1 positive input source select reg<1168> 0: io8 1: acmp0 in+ source acmp1 analog buffer enable (max. band width 1 mhz) reg<1169> 0: disable analog buffer 1: enable analog buffer acmp1 hysteresis enable reg<1171:1170> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) (01: for both external & internal vref; 10 & 11: for only inter nal vref; external vref will not have 50 mv & 200 mv hysteresis) acmp1 wake & sleep function enable reg<1491> 0: disable 1: enable acmp1 negative input voltage select reg<1636:1632> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: pin10: ext_vref 11011: pin10: ext_vref 11100: pin10: ext_vref/2 11101: pin10: ext_vref/2 acmp1 positive input divider reg<1638:1637> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp1 low bandwidth (max: 1 mhz) enable reg<1639> 0: off 1: on
SLG46536_ds_105 page 97 of 164 SLG46536 10.5 acmp2 block diagram figure 57. acmp2 block diagram internal vref from acmp0s mux output pin4 selectable gain reg <1646:1645> vref + - from connection matrix output <53> pdb lbw selection reg <1647> hysteresis selection reg <1182:1181> l/s to connection matrix input<59> reg <1644:1640> bg_ok latch 0 1 reg <1492> acmp2 wake & sleep function enable 11010 11011 11100 11101 11001- 00000 pin10: ext_vref reserved reserved pin10: ext_vref/2
SLG46536_ds_105 page 98 of 164 SLG46536 10.6 acmp2 register settings table 85. acmp2 register settings signal function register bit address register definition acmp2 hysteresis enable reg<1182:1181> 00: disabled (0 mv) 01: enabled (25 mv) 10: enabled (50 mv) 11: enabled (200 mv) (01: for both external & internal vref; 10 & 11: for only inter nal vref; external vref will not have 50 mv & 2 00 mv hysteresis) acmp2 wake & sleep function enable reg<1492> 0: disable 1: enable acmp2 negative input voltage select reg<1644:1640> 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: pin10: ext_vref 11011: reserved 11100: pin10: ext_vref/2 11101: reserved acmp2 positive input divider reg<1646:1645> 00: 1.00x 01: 0.50x 10: 0.33x 11: 0.25x acmp2 low bandwidth (max: 1 mhz) enable reg<1647> 0: off 1: on
SLG46536_ds_105 page 99 of 164 SLG46536 11.0 pipe delay (pd) the SLG46536 has a pipe delay logic cell that is shared with th e 3-bit lut10 in one of the combination function macrocells. th e user can select one of these func tions to use in a design, but not both. please see section 9.4 3-bit lut or pipe delay macrocell for the description of this combination function macrocell.
SLG46536_ds_105 page 100 of 164 SLG46536 12.0 programmable delay / edge detector the SLG46536 has a programmable time delay logic cell available that can generate a delay that is selectable from one of four timings configured in the greenpak designer. the programmable t ime delay cell can generate one of four different delay pattern s, rising edge detection, falling edge detection, both edge detect ion and both edge delay. see the timing diagrams below for furt her information. note : the input signal must be longer than the delay, otherwise it will be filtered out. 12.1 programmable delay timing diagram - edge detector output please refer to table 4. expected delays and widths (typical) figure 58. programmable delay figure 59. edge detector output programmable delay out in reg <1267:1266> from connection matrix output <57> to connection matrix input <61> reg <1265:1264> edge mode selection delay value selection time1 edge detector output in rising edge detector falling edge detector both edge detector both edge delay time1 time1 is a fixed value time2 delay value is selected via register time2 time2 width width
SLG46536_ds_105 page 101 of 164 SLG46536 12.2 programmable dela y register settings table 86. programmable de lay register settings signal function register bit address register definition select the edge mode of programmable delay & edge detector reg<1265:1264> 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay delay value select for programmable delay & edge detector (vdd = 3.3 v, typical condition) reg<1267:1266> 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns
SLG46536_ds_105 page 102 of 164 SLG46536 13.0 additional logic functions the SLG46536 has two additional logic functions that are connec ted directly to the connection m atrix inputs and outputs. there are two deglitch filters, each with edge detector functions. 13.1 deglitch filter / edge detector 13.2 deglitch filter register settings figure 60. deglitch filter / edge detector table 87. programmable de lay register settings signal function register bit address register definition filter_1/edge detector_1 edge select reg<1457:1456> 00: rising edge detector 01: fall edge detector 10: both edge detector 11: both edge delay filter_1/edge detector_1 output polarity select reg<1458> 0: filter_1 output 1: filter_1 out put inverted filter_1 or edge detector_1 select (typ. 30 ns @vdd=3.3v) reg<1459> 0: filter_1 1: edge detector_1 filter_0/edge detector_0 edge select reg<1461:1460> 00: rising edge detector 01: fall edge detector 10: both edge detector 11: both edge delay from connection matrix output <55> to connection matrix input <30> from connection matrix output <56> to connection matrix input <31> filter_0 filter_1 reg <1462> reg <1458> c c r r reg <1463> reg <1459> edge detect edge detect edge select reg <1457:1456> edge select reg <1461:1460>
SLG46536_ds_105 page 103 of 164 SLG46536 filter_0/edge detector_0 output polarity select reg<1462> 0: filter_0 output 1: filter_0 out put inverted filter_0 or edge detector_0 select (typ. 47 ns @vdd=3.3v) reg<1463> 0: filter_0 1: edge detector_0 table 87. programmable de lay register settings signal function register bit address register definition
SLG46536_ds_105 page 104 of 164 SLG46536 14.0 voltage reference (vref) 14.1 voltage reference overview the SLG46536 has a voltage reference macrocell to provide refer ences to the four analog comparators. this macrocell can supply a user selectio n of fixed voltage references, /3 and /4 reference off of the v dd power supply to the dev ice, and externally supplied voltage references from pins 5 and 11. see table below for the available selections for each analog comparator. also see figure 61 below, which shows the re ference output structure. 14.2 vref selection table table 88. vref selection table sel<4:0> acmp0_vref acmp1_vref acmp2_vref 11101 pin 5: acmp0(-)/2 pin 10: acmp1(-)/2 pin 11: acmp2(-)/2 11100 pin 10: acmp0(-)/2 pin 1 0: acmp1(-)/2 pin 10: acmp2(-)/2 11011 pin 5: acmp0(-) pin 10: acmp1(-) pin 11: acmp2(-) 11010 pin 10: acmp0(-) pin 10: acmp1(-) pin 10: acmp2(-) 11001 vdd / 4 vdd / 4 vdd / 4 11000 vdd / 3 vdd / 3 vdd / 3 10111 1.20 1.20 1.20 10110 1.15 1.15 1.15 10101 1.10 1.10 1.10 10100 1.05 1.05 1.05 10011 1.00 1.00 1.00 10010 0.95 0.95 0.95 10001 0.90 0.90 0.90 10000 0.85 0.85 0.85 01111 0.80 0.80 0.80 01110 0.75 0.75 0.75 01101 0.70 0.70 0.70 01100 0.65 0.65 0.65 01011 0.60 0.60 0.60 01010 0.55 0.55 0.55 01001 0.50 0.50 0.50 01000 0.45 0.45 0.45 00111 0.40 0.40 0.40 00110 0.35 0.35 0.35 00101 0.30 0.30 0.30 00100 0.25 0.25 0.25 00011 0.20 0.20 0.20 00010 0.15 0.15 0.15 00001 0.10 0.10 0.10 00000 0.05 0.05 0.05 vdd practical vref range note 2.0 v - 5.5 v 50 mv ~ 1.2 v 1.7 v - 2.0v 50 mv ~ 1.0 v do not operate above 1.0 v
SLG46536_ds_105 page 105 of 164 SLG46536 14.3 vref block diagram figure 61. voltage refe rence block diagram acmp0_vref acmp1_vref acmp2_vref acmp3_vref reg <1628:1624> reg <1636:1632> reg <1644:1640> reg <1652:1648> vdd / 3 vdd / 4 ext_vref_acmp1 (pin10) ext_vref_acmp0 (pin5) reg <1476> reg <1474> vdd / 2 vdd / 3 vdd / 4
SLG46536_ds_105 page 106 of 164 SLG46536 15.0 rc oscillator (rc osc) the SLG46536 has three internal o scillators. rc oscillator that runs at 25 khz / 2 mhz (osc0), oscillator that runs at 25 mhz (osc1) and crystal oscillator. it is possible to use all three oscillators simultaneously. the fundamental frequency can also come from clock input (pin 14 for 25 k hz / 2 mhz and pin 13 for 25 m hz or crystal osc), see section 19.0 external clocking . 15.1 25 khz/2 mhz and 25 mhz rc oscillators there are two divider stages that allow the user flexibility fo r introducing clock signals on various connection matrix input lines. the predivider allows the selection of /1, /2, /4 or /8 divide down frequency from the fundamental. the second stage divider ( only for 25 khz / 2 mhz oscillator) has an input of frequency from t he predivider, and outputs one of seven different frequencies o n connection matrix input lines <27> (out0) and <28> (out1). see figure 62 and figure 63 below for details. there are two modes of the power control pin, (reg<1658> for 25 khz / 2 mhz osc and reg<1657> for 25 mhz osc): ? power down <0> . if pwr control input of oscillator is low, the oscillator wil l be turned on. if pwr control input of oscillator is high the oscill ator will be turne d off and osc divider will reset. ? force on <1> . if pwr control input of oscilla tor is high, the oscillator wi ll be turned on. if pwr control input of oscillator is low the osci llator will be turned off. the pwr control signal has the highest priority. the SLG46536 has a 25 khz / 2 mhz osc fast start-up function re g<1338> (1 C on, 0 C off). it allows the osc to run immediately after power-up. start-up time is less than one cycl e. note that when osc fast start-up is on, the current consumption will rise. the user can select two osc powe r modes (reg<1343 for 25 khz / 2 mhz osc and reg<1341> for 25 mhz osc): ?if auto power on <0> is selected, the osc will run only when any macr ocell that use s osc is powered on. ?if force power on <1> is selected, the osc will run when the sl g46536 is powered on. osc can be turned on by: ? register control (force power on) ? delay mode, when delay requires osc ? cnt/fsm
SLG46536_ds_105 page 107 of 164 SLG46536 figure 62. 25 khz / 2 mh z rc osc block diagram figure 63. 25 mhz rc osc block diagram internal rco reg <1342> 0: 25 khz 1: 2 mhz pin 14 ext. clock ext. clk sel reg <1358> / 2 / 3 / 4 / 8 / 12 / 24 / 64 0 1 2 3 4 5 6 7 to connection matrix input <27> reg <1349:1347> div /1 /2 /4 /8 reg <1340:1339> predivider second stage divider 0 1 from connection matrix output <58> pwr down to connection matrix input <28> reg <1346:1344> auto power on 0 1 force power on osc power mode reg <1343> out0 out1 internal rco 25 mhz osc pin 13 ext. clock ext. clk sel reg <1357> to connection matrix input <29> div /1 /2 /4 /8 reg <1337:1336> divider 0 1 from connection matrix output <59> pwr down auto power on 0 1 force power on osc power mode reg <1341> out
SLG46536_ds_105 page 108 of 164 SLG46536 15.2 oscillator power on delay figure 64. oscillator startup diagram figure 65. rc oscillator maximum p ower on delay vs. vdd at room temperature, osc0 = 2 mhz 1rwh? osc power mode: "auto power on. note 2: osc enable signal appears when any block that uses osc is powe red on. 150 250 350 450 550 650 750 850 950 1,050 1.7 1.8 1.9 2.3 2.5 2.7 3.0 3.3 3.6 4.2 4.5 5.0 5.5 power on delay (ns) vdd (v) normal start-up mode fast start-up mode
SLG46536_ds_105 page 109 of 164 SLG46536 figure 66. rc oscillator maximum power on delay vs. vdd at room temperature, osc0 = 25 khz figure 67. osc1 (25 mhz) maximum power on delay vs. vdd at room temperature 0 5 10 15 20 25 1.7 1.8 1.9 2.3 2.5 2.7 3.0 3.3 3.6 4.2 4.5 5.0 5.5 power on delay ( s) vdd (v) normal start-up mode fast start-up mode 0 1 2 3 4 5 6 7 8 9 1,71 1,8 1,89 2,3 2,5 2,7 3 3,3 3,6 4,2 4,5 5 5,5 power on delay (s) vdd (v)
SLG46536_ds_105 page 110 of 164 SLG46536 15.3 oscillator accuracy note: osc power setting: force power on; clock to matrix input - enable; bandgap: turn on by register - enable. figure 68. rc oscillator frequency vs. temperature, rc osc0=2 mh z figure 69. rc oscillator frequency vs. temperature, rc osc0=25 k hz 1.75 1.8 1.85 1.9 1.95 2 2.05 2.1 2.15 2.2 -40 -20 0 20 40 60 80 f (mhz) t (c) fmax @ vdd=1.8 v fmin @ vdd=1.8 v fmax @ vdd=3.3 v fmin @ vdd=3.3 v fmax @ vdd=5.0 v fmin @ vdd=5.0 v 23.5 24 24.5 25 25.5 26 26.5 27 -40 -20 0 20 40 60 80 f (khz) t (c) fmax @ vdd=1.8 v fmin @ vdd=1.8 v fmax @ vdd=3.3 v fmin @ vdd=3.3 v fmax @ vdd=5.0 v fmin @ vdd=5.0 v
SLG46536_ds_105 page 111 of 164 SLG46536 note 1: for more information see section 5.11 osc specifications. note 2: 25 mhz rc osc1 performance is not guaranteed at vdd < 2.5 v. figure 70. osc1 (25 mhz) frequency vs. temperature 17 19 21 23 25 27 29 31 -40 -20 0 20 40 60 80 f (mhz) t (c) fmax @ vdd=1.8 v fmin @ vdd=1.8 v fmax @ vdd=3.3 v fmin @ vdd=3.3 v fmax @ vdd=5.0 v fmin @ vdd=5.0 v
SLG46536_ds_105 page 112 of 164 SLG46536 16.0 crystal oscillator the crystal osc provides high precision and stability of the ou tput frequency. pin 13 and pin 12 are input and output, respect ively, of an inverting amplifier which is configured for use as an on- chip oscillator, as shown in figure 72 . either a quartz crystal or a ceramic resonator may be used. the optimal value of the capacit ors depends on the crystal or r esonator in use, the amount of stray capacitance, and the elec tromagnetic noise of the environ ment. refer to table 89 . for the ceramic resonators, the capacitor values given by the manufacturer should be used. it is possible to use an external clock source , it must be conne cted to pin 1 3. in this case no external components are required. figure 71. crystal osc block diagram figure 72. external crystal connection table 89. external components selection table f c1 c2 r1 r2 32.768 khz 10 pf 330 pf 20 m ? 20 k ? 4 - 40 mhz 12 pf 12 pf 1 m ? 0 ? crystal osc to connection matrix input <53> from connection matrix output <109> pwr down disable 0 1 enable osc power mode reg <1136> pin 13 pin 12 out crystal SLG46536 pin 13 pin 12 c2 c1 r1 r2
SLG46536_ds_105 page 113 of 164 SLG46536 17.0 power on reset (por) the SLG46536 has a power-on reset (por) macrocell to ensure cor rect device initialization and operation of all macrocells in the device. the purpose of the por circuit is to have consisten t behavior and predictable results when the vdd power is first ramping to the device, and also while the vdd is falling during power-down. to accomplish this goal, the por drives a defined sequence of internal events that trigger changes to the states of different macrocells inside th e device, and finally to the s tate of the i/o pins. 17.1 general operation the SLG46536 is guaranteed to be powered down and nonoperationa l when the vdd voltage (voltage on pin1) is less than power off threshold (see in electrical characteristics table), but not less than -0.6 v. another essential condition for the c hip to be powered down is that no voltage higher (see note 1) than the vdd voltage is applied to any other pin. for example, if vdd voltage is 0.3 v, applying a voltage higher than 0.3 v to any o ther pin is incorrect, and can lead to incorrect or unexpected device behavior. note 1. there is a 0.6 v margin due to forward drop voltage of the esd protection diodes. to start the por sequence in the SLG46536, the voltage applied on the vdd should be higher than the power_on threshold (see note 2). the full operational vdd range for the SLG46536 i s 1.71 v C 5.5 v (1.8 v 5 % - 5 v 10 %). this means that th e vdd voltage must ramp up to the operational voltage value, but the por sequence will start earlier, as soon as the vdd voltage rises to the power_on threshold. after the por sequence has sta rted, the SLG46536 will have a typical period of time to go through all the steps in the s equence (noted in the datasheet f or that device), and will be r eady and completely operational a fter the por sequence is complete. note 2. the power_on threshold is defined in electrical characteristics table. to power down the chip the vdd voltage should be lower than the operational and to guarantee that chip is powered down it should be less than power off threshold. all pins are in high impedance st ate when the chip is powered d own and while the por sequence is taking place. the last step in the por sequence releases the i/o structures from the high i mpedance state, at which time the device is operational. the pi n configuration at this point in time is defined by the design pr ogrammed into the chip. also as it was mentioned before the vol tage on pins cant be bigger than t he vdd, this rule also applies to the case when the chip is powered on.
SLG46536_ds_105 page 114 of 164 SLG46536 17.2 por sequence the por system generat es a sequence of signa ls that enable cert ain macrocells. the sequence is shown in figure 73 . as can be seen from figure 73 after the vdd has start ramping up and crosses the power_on th reshold, first, the on-chip nvm memory is reset. next the chip reads the data from nvm, and tra nsfers this information to sram registers that serve to configu re each macrocell, and the connection matrix which routes signals between macrocells. the third stage causes the reset of the inp ut pins, and then to enable them. after that, the luts are reset a nd become active. after luts the delay cells, rc osc, dffs, latches and pipe delay are initialized. only after all macrocel ls are initialized internal por s ignal (por macrocell output) g oes from low to high. the last portion of the device to be initiali zed are the output pins, which transition from high impedience to active at this point. the typical time that takes to complete the por sequence varies by device type in the greenpak family. it also depends on many environmental factors, such as: slew rate, vdd value, temperatu re and even will vary from chip to chip (process influence). figure 73. por sequence vdd por_nvm (reset for nvm) nvm_ready_out por_gpi (reset for input enable) por_lut (reset for lut output) por_core (reset for dly/rco/dff /latch/pipe dly por_out (generate low to high to matrix) por_gpo (reset for output enable) t t t t t t t t input: ignore transition output: initial state (determined by reg<1354:1352>)
SLG46536_ds_105 page 115 of 164 SLG46536 17.3 macrocells output states during por sequence to have a full picture of SLG46536 operation during powering an d por sequence, review the overview the macrocell output states during the por sequence ( figure 74 describes the output signals states). first, before the nvm has been res et, all macrocells have their output set to logic low (exc ept the output pins which are in h igh impedance state). before the nv m is ready, all macrocell output s are unpredictable (except the output pins). on the next step, some of the macrocells start ini tialization: input pins output state becomes low; luts also output low. only p dly macrocell configured as edge detector becomes active at this time. after that input pins are enabled. next, only luts are configured. ne xt, all other macrocells are initialized. after macrocells are init ialized, internal por matrix signa l switches from low to high. the last are output pins that become active and determined by the i nput signals. figure 74. internal macrocell states during por sequence unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable unpredictable vdd input pin_out to matrix lut_out to matrix programmable delay_out to matrix prog. edge_detector_out to matrix dff/latch_out to matrix delay_out to matrix por_out to matrix ext. gpo vdd_out to matrix determined by input signals determined by input signals starts to detect input edges determined by input signals determined by input signals determined by input signals starts to detect input edges determined by input signals determined by external signal guaranteed high before por_gpi determined by input signals out = in without delay determined by initial state determined by input signals out = in without delay tri-state t t t t t t t t t t output state unpredictable
SLG46536_ds_105 page 116 of 164 SLG46536 17.3.1 initialization all internal macrocells by default have initial low level. star ting from indicated powerup time of 1.15 v - 1.6 v, macrocells in gpak5 are powered on while forced to the reset state, all outputs are in hi-z and chip starts loading data from nvm. then the reset signal is released for internal macrocells and they start to initializ e according to the following sequence: 1. i 2 c; 2. input pins, acmp , pull up/down; 3. luts; 4. dffs, delays/counters, pipe delay; 5. por output to matrix; 6. output pin corresponds to the internal logic the por signal going high indica tes the mentioned powerup sequ ence is complete. note: the maximum voltage applied to any pin should not be hi gher than the vdd level. t here are esd diodes between pin ? > vdd and pin ?> gnd on each pin. so if the input signal applied to pin is higher than vdd, then current will sink through the diode to vdd. exceeding vdd results in leakage current on the input pin, and vdd will be pulled up, following the voltage on the input pin.there is no ef fect from input pin when input voltage is applied at the same time as vdd. 17.3.2 power down during powerdown, macrocells in SLG46536 are powered off after vdd falling down below power off threshold. please note that during a slow rampdown, outp uts can possibly switch state during this time. figure 75. power down not guaranteed output state vdd (v) time 1.6 v 1.15 v 2 v 1 v 1 v vref out signal
SLG46536_ds_105 page 117 of 164 SLG46536 18.0 i 2 c serial communications macrocell 18.1 i 2 c serial commu nications macrocell overview in the standard use case for t he greenpak devices, the configur ation choices made by the user are stored as bit settings in th e non-volatile memory (nvm), and this information is transferred at startup time to volatile ram registers that enable the confi gu- ration of the macrocells. other ram registers in the device are responsible for setting the connections in the connection matr ix to route signals in th e manner most appropri ate for the users application. the i 2 c serial communications macrocell in this device allows an i 2 c bus master to read and write this information via a serial channel directly to the ram registers, allowing the remote re-c onfiguration of macrocells, and remote changes to signal chains within the device. an i 2 c bus master is also able read and write other register bits th at are not associated with nvm memory. as an example, the input lines to the connection matrix can be read as digital reg ister bits. these are the signal outputs of each of the macroce lls in the device, giving an i 2 c bus master the capability to re motely read the current value of any macrocell. the user has the flexibility to control read access and write a ccess via registers bits reg<1832>, reg<1870>, and reg<1871>. s ee section 18.5 i2c serial command register protection for more details on i 2 c read/write memory protection. note: greenpak i 2 c is fully compatible with standard i 2 c protocol. 18.2 i 2 c serial communicati ons device addressing each command to the i 2 c serial communications macrocell begins with a control byte. t he bits inside this control byte are shown in figure 76 . after the start bit, the first four bits are a control code, which can be set by the user in reg<1867:1864>. this gives the user flexibility on the chip level addressing of this device and other devices on the same i 2 c bus. the block address is the next three bits (a10,a9, a8 ), which will define the most si gnificant bits in the addressing of the data to be read or writ ten by the command. the last bit in the control byte is the r/w bit, which selects whether a read command or write command is requested, with a 1 selecti ng for a read command, and a 0 s electing for a write command. this control byte will be followe d by an acknowledge bit (ack), whic h is sent by this device to in dicate successful communication of the control byte data. in the i 2 c-bus specification and user manual, there are two groups of ei ght addresses (0000 xxx and 1111 xxx) that are reserved for the special functions, such as a system general call addres s. if the user of this device choses to set the control code to either 1111 or 0000 in a system with other slave device, please co nsult the i 2 c-bus specification and user manual to understand the addressing and implementation o f these special functions, to in sure reliable operation. in the read and write command address structure, there are a to tal of 11 bits of addressing, each pointing to a unique byte of information, resulting in a tota l address space of 2k bytes. of this 2k byte address space, the valid addresses accessible to the i 2 c macrocell on the SLG46536 are in the range from 0 (0x00) to 2 55 (0xff). the msb address bits (a10, a9 and a8) will be 0 for all commands to the SLG46536. with the exception of the current address read command, all com mands will have the control byte followed by the word address. figure 76 shows this basic co mmand structure. figure 76. basic command structure x x x x a 1 0 a 9 a 8 r/w a 7 a 0 control byte word address control code block address read/write bit (1 = read, 0 = write) s ack acknowledge bit start bit n o t u s e d , s e t t o 0
SLG46536_ds_105 page 118 of 164 SLG46536 18.3 i 2 c serial general timing general timing characteristics for the i 2 c serial communications macrocell are shown in figure 77 . timing specifications can be found in the ac charac teristics section. 18.4 i 2 c serial communi cations commands 18.4.1 byte write command following the start condition from the master, the control code [4 bits], the block address [3 bits] and the r/w bit (set to 0), are placed onto the i 2 c bus by the master. after the SLG46536 sends an acknowledge bi t (ack), the next byte transmitted by the master is the word address. the block address (a10, a9, a8), co mbined with the word address (a7 through a0), together set the internal address pointer in the SLG46536 where the data byt e is to be written. after the SLG46536 sends another acknowledg e bit, the master will transmit the data byte to be written into the addressed memory location. the SLG46536 again provides an acknowledge bit and then the mas ter generates a stop condition. the internal write cycle for t he data will take place at the t ime that the SLG46536 generates the acknowledge bit. figure 77. i 2 c general timing characteristics figure 78. byte write command, r/w = 0 scl t f t r t su sto t buf t high t low t su dat t hd dat t hd sta t su sta t aa t dh sda in sda out x x x x a 1 0 a 9 a 8 w a 7 a 0 control byte word address control code block address r/w bit = 0 s ack acknowledge bit start bit ack d 7 d 0 data p stop bit acknowledge bit sda line bus activity acknowledge bit ack n o t u s e d , s e t t o 0
SLG46536_ds_105 page 119 of 164 SLG46536 18.4.2 sequential write command the write control byte, word a ddress and the first data byte ar e transmitted to the SLG46536 in the same way as in a byte writ e command. however, instead of generating a stop condition, the m aster continues to transmit data bytes to the SLG46536. each subsequent data byte will incre ment the internal address counte r, and will be written into the next higher byte in the command addressing. as in the case of the byte write command, the inter nal write cycle will take place at the time that the SLG46536 generates the acknowledge bit. 18.4.3 current address read command the current address read command reads from the current pointer address location. the address pointer is incremented at the first stop bit following any write control byte. for example, i f a write or random read (which contains a write control byte) writes or reads data up to address n, t he address pointer would get in cremented to n+1 upon the stop of that command. subsequently, a current address read that follows would start reading data at n+1. the current address read command contains the control byte sent by the master, with the r/w bit = 1. the SLG46536 will issue an acknowledge bit, and the n transmit eight data bits for the requested byte. the master will not issue an acknowledg e bit, and follow immediately with a stop condition. figure 79. sequential write command, r/w = 0 figure 80. current address read command, r/w = 1 x x x x a 1 0 a 9 a 8 w control byte word address (n) control code block address r/w bit = 0 s ack acknowledge bit start bit data (n) stop bit sda line bus activity ack data (n + 1) ack ack data (n + x) p acknowledge bit ack n o t u s e d , s e t t o 0 x x x x a 1 0 a 9 a 8 r control byte data (n) control code block address r/w bit = 1 s ack acknowledge bit start bit p stop bit no ack bit sda line bus activity n o t u s e d , s e t t o 0 nack
SLG46536_ds_105 page 120 of 164 SLG46536 18.4.4 random read command the random read command starts with a control byte (with r/w bit set to 0, indicating a wr ite command) and word address to set the internal byte address, followed by a start bit, and then the control byte for the read (exactly the same as the byt e write command). the start bit in the middle of the command will halt the decoding of a write command, but will set the internal addr ess counter in preparation for the second half of the command. afte r the start bit, the master issu es a second control byte with t he r/w bit set to 1, after which t he SLG46536 issues an acknowledge bit, followed by the reque sted eight data bits. 18.4.5 sequential read command the sequential read command is initiated in the same way as a c urrent address read or random read command, except that once the SLG46536 transmits the first data byte, the master iss ues an acknowledge bit as opposed to a stop condition in a rand om read. the master can continue r eading sequential bytes of data, and will terminate the comma nd with a stop condition. figure 81. random read command figure 82. sequential read command x x x x a 1 0 a 9 a 8 w control byte word address (n) control code block address r/w bit = 0 s ack acknowledge bit start bit control byte stop bit sda line bus activity ack data (n) ack p xxxx a 1 0 a 9 a 8 r s r/w bit = 1 no ack bit n o t u s e d , s e t t o 0 control code x x x x a 1 0 a 9 a 8 r control byte data (n) control code block address r/w bit = 1 s ack acknowledge bit start bit data (n+1) stop bit sda line bus activity ack data (n + 2) ack ack data (n + x) p no ack bit n o t u s e d , s e t t o 0
SLG46536_ds_105 page 121 of 164 SLG46536 18.4.6 i 2 c serial command register map these register addresses are broken down into four banks to giv e the user greater control on access to reading and writing information in each bank. each of the four banks is 512 bits (6 4 bytes) in length. writing information to register bits in the se banks will change the configuration of t he device, resulting in eithe r a change in the interconnection options provided by the conne ction matrix, or by changing the configuration of individual macrocel ls. during device use, all regist er bits can be read or written via i 2 c, unless protection bits are set to prevent this. see section 20.0 appendix a - SLG46536 register definition for detailed in formation on all register bits 18.5 i 2 c serial command register protection the memory space is divided into four banks, each of which has 512bits (64bytes). there are thr ee bits that allow the user to define rules for reading and writi ng bits in each of these bank s via i 2 c: ? reg<1832> i 2 c lock for read bits <1535:0> ( bank 0/1/2). if the system provi des any read commands to the addresses in these three banks, the device will res pond with ffh in data field. ? reg<1871> i 2 c lock for write bits <1535:0> ( bank 0/1/2). if the system prov ides any write commands to the addresses in these three banks, the device wi ll acknowledge these commands, but will not do internal write s to the register space. ? reg<1870> i 2 c lock for write all bits (bank 0/1/2/3). if the system provide s any write commands to the add resses in these four banks, the device will ack nowledge these commands, but wil l not do internal write s to the register space. note 1. reg<1870> is higher priority than reg<1871>, and if reg<1870> is set, than reg<1871> does not have any effect. note 2. if the user sets pins 8 and 9 function to a selection other than sda and scl, all access via i 2 c will be disabled. if reg <1870> is not set, register bits in bank 3 are open to r ead and write commands via i 2 c with the following exceptions: ? reg<1663> io latching enable dur ing i2c write interface is alw ays protected from i 2 c write, see note 3. ? reg<1871> bank 0/1/2 i 2 c-write protection bit i s always protected from i 2 c write ? reg<1867:1864> i 2 c control code bit [3:0] i s always protected from i 2 c write note 3. if reg<1663> = 1, all outputs are latched while inpu ts and internal macrocells retain their status during i 2 c write. note 4. any write commands that come to the device via i 2 c that are not blocked, based on the protection bits, will change the contents of the ram register bits that mirror the nvm bits. these write commands will not change the nvm bits themselves, and a por event will restore the register bits to original programmed contents of the nvm. figure 83. register bank map byte 0 bank 0 bank 1 bank 2 bank 3 byte 63 byte 64 byte 127 byte 128 byte 191 byte 192 byte 255
SLG46536_ds_105 page 122 of 164 SLG46536 see section 20.0 appendix a - SLG46536 register definition for detailed information on all registers. 18.5.1 register read/write protection there are six read/write protec t modes for the design sequence from being corrupted or copied. see table 90 for details. table 90. read/write protection options bank byte bits description lock status unlocked locked for read bits <1535:0> locked for write bits <1535:0> locked for write all bits locked for read and write bits <1535:0> locked for read bits <1535:0> and write all bits reg <1832>=0, <1871>=0, <1870>=0 reg <1832>=1, <1871>=0, <1870>=0 reg <1832>=0, <1871>=0, <1870>=0 reg <1832>=0, <1871>=x, <1870>=1 reg <1832>=1, <1871>=1, <1870>=0 reg <1832>=1, <1871>=x, <1870>=1 0 0-63 511-0 connection matrix outputs configuration r/w w r r - - 1 64-109 879-512 r/w w r r - - 110-127 880-1023 reserved - - - - - - 2 128-186 1495-1024 function configuration for pins, luts/dffs, osc, asm and some configuration for dlys, acmp r/w w r r - - 187-191 1535-1496 reserved - - - - - - 3 192-206 1655-1536 cnt/dly counter data and some luts truth table, acmp vref r/w r/w r/w r r/w r 207 1663 io latching enable during i2c write interface r r r r r r 1662 i2c reset bit with reloading nvm into data register r/w r/w r/w r r/w r 1661-1659 reserved r r r r r r 1658-1656 osc power control r/w r/w r/w r r/w r
SLG46536_ds_105 page 123 of 164 SLG46536 3 208-223 1791-1664 asm output ram and user configurable ram / otp r/w r/w r/w r r/w r 224-227 1823-1792 reserved - - - - - - 228 1831-1824 reserved r/w r/w r/w r r/w r 229 1839-1836 product family id r r r r r r 1835-1834 reserved - - - - - - 1833 reserved r r r r r r 1832 i2c lock for read bits<1535:0> r r r r r r 230 1847-1840 pattern id r/w r/w r/w r r/w r 231 1855-1848 reserved r r r r r r 232 1863-1856 reserved r r r r r r 233 1871 i2c lock for write bits<1535:0> r r r r r r 1870 i2c lock for write all bits r r r r r r 1869-1868 reserved - - - - - - 1867-1864 i2c control code r r r r r r 234-239 1919-1872 counter current value r r r r r r 240-243 1951-1920 macrocells output values (connection matrix inputs) r r r r r r 244 1959-1952 connection matrix virtual inputs r/w r/w r/w r r/w r 245-247 2007-1983 macrocells output values (connection matrix inputs) r r r r r r 248-250 2007-1984 reserved r r r r r r table 90. read/write protection options bank byte bits description lock status unlocked locked for read bits <1535:0> locked for write bits <1535:0> locked for write all bits locked for read and write bits <1535:0> locked for read bits <1535:0> and write all bits reg <1832>=0, <1871>=0, <1870>=0 reg <1832>=1, <1871>=0, <1870>=0 reg <1832>=0, <1871>=0, <1870>=0 reg <1832>=0, <1871>=x, <1870>=1 reg <1832>=1, <1871>=1, <1870>=0 reg <1832>=1, <1871>=x, <1870>=1
SLG46536_ds_105 page 124 of 164 SLG46536 18.5.1.1 i 2 c serial reset command if i 2 c serial communication is established with the device, it is po ssible to reset the device to initial power up conditions, incl uding configuration of all macrocells , and all connections provided b y the connection matrix. this is implemented by setting reg<166 2> i 2 c reset bit to 1, which causes the device to re-enable the po wer on reset (por) sequence, including the reload of all regist er data from nvm. during the por sequence, the outputs of the devi ce will be in tri-state. after the reset has taken place, the c ontents of reg<1662> will be set to 0 automatically. the timing diagr am shown below illustrates the s equence of events for this rese t function. note: i 2 c serial reset command is not available during emulation. 3 251 2015-2008 reserved r/w r/w r/w r r/w r 252-253 2031-2016 reserved r r r r r r 254 2039-2032 reserved r/w r/w r/w r r/w r 255 2047-2040 reserved r/w r/w r/w r r/w r r/w allow read and write data w allow write data only r allow read data only - the data is protected for read and write table 90. read/write protection options bank byte bits description lock status unlocked locked for read bits <1535:0> locked for write bits <1535:0> locked for write all bits locked for read and write bits <1535:0> locked for read bits <1535:0> and write all bits reg <1832>=0, <1871>=0, <1870>=0 reg <1832>=1, <1871>=0, <1870>=0 reg <1832>=0, <1871>=0, <1870>=0 reg <1832>=0, <1871>=x, <1870>=1 reg <1832>=1, <1871>=1, <1870>=0 reg <1832>=1, <1871>=x, <1870>=1
SLG46536_ds_105 page 125 of 164 SLG46536 figure 84. reset command timing x x x x a 1 0 a 9 a 8 w a 7 a 0 control byte word address control code block address write bit s ack acknowledge bit start bit ack d 7 d 0 data p stop bit acknowledge bit sda line bus activity acknowledge bit ack reset-bit register output reloading nvm into data register internal por internal reset bit by i 2 c stop signal reset-bit register (reg<1662>) is cleared by reloading nvm into data register 1) i 2 c write with reg<1662>=1 (i 2 c reset bit with reloading nvm into data register) 2) por go to low and reloading nvm into data register start aft er stop of i 2 c 3) por go to high after reloading nvm into data register n o t u s e d , s e t t o 0
SLG46536_ds_105 page 126 of 164 SLG46536 18.5.1.2 reading counter data via i 2 c the current count value in four counters in the device can be r ead via i 2 c. the counters that have this additional functionality are 16-bit cnt0 and cnt1, and 8 -bit counters cnt4 and cnt6. 18.5.1.3 user ram and otp memory array there are eight bytes of ram memory that can be read and writte n remotely by i 2 c commands. the initial contents of this memory space can be selected by the u ser, and this information will be transferred from otp memory t o the ram memory space during the power-up sequence. the lowest order byte in this array (use r configurable ram/otp byte 0) is located at i 2 c address 0xd8, and the highest order byte i n this array is located at i 2 c address 0xdf. table 91. ram array table i2c address (hex) highest bit address lowest bit address memory byte d8 1735 1728 user configurable ram/otp byte 0 d9 1743 1736 user configurable ram/otp byte 1 da 1751 1744 user configurable ram/otp byte 2 db 1759 1752 user configurable ram/otp byte 3 dc 1767 1760 user configurable ram/otp byte 4 dd 1775 1768 user configurable ram/otp byte 5 de 1783 1776 user configurable ram/otp byte 6 df 1791 1784 user configurable ram/otp byte 7
SLG46536_ds_105 page 127 of 164 SLG46536 19.0 external clocking the SLG46536 supports several wa ys to use an external, higher a ccuracy clock as a reference so urce for internal operations. 19.1 crystal mode when reg<1136> is set to 1, an external crystal can be connecte d to pins 12 and 13 for supplying an accurate clock source. see section 16.0 crystal oscillator . an external clocking signal on pin 13 can be used in place of the crystal. the high and low limits for crystal frequency that can be s elected are 32. 768 khz and 4 0 mhz. 19.2 pin 14 source for 25 khz / 2 mhz clock when reg<1358> is set to 1, an external clocking signal on pin 14 will be routed in place of the internal rc oscillator derive d 25 khz/2 mhz clock source. see figure 62 . reg<1355> must be set to 0. the high and low limits for external frequency that can be selected are 0 mhz and 77 mhz. 19.3 pin 13 source for 25 mhz clock when reg<1357> is set to 1, an external clocking signal on pin 13 will be routed in place of the internal rc oscillator derive d 25 mhz clock source. see figure 63 . the high and low limits for external frequency that can be se lected are 0 mhz and 84 mhz.
SLG46536_ds_105 page 128 of 164 SLG46536 20.0 appendix a - SLG46536 register definition address signal function register bit definition i 2 c interface byte register bit read write note: for reg<0> to reg<1495>, i 2 c read is valid (assuming reg <1832> = 0), i 2 c write is valid (assuming reg <1871> = 0) matrix output 00 reg<5:0> matrix out in0 of lut3_11 o r clock input of dff8 valid valid reg<7:6> reserved valid valid 01 reg<13:8> matrix out in1 of lut3_11 or data input of dff8 valid val id reg<15:14> reserved valid valid 02 reg<21:16> matrix out in2 of lut3_11 or rstb (setb) of dff8 valid valid reg<23:22> reserved valid valid 03 reg<29:24> matrix out in0 of lut3_12 o r clock input of dff9 valid valid reg<31:30> reserved valid valid 04 reg<37:32> matrix out in1 of lut3_12 or data input of dff9 valid v alid reg<39:38> reserved valid valid 05 reg<45:40> matrix out in2 of lut3_12 or rstb (setb) of dff9 valid valid reg<47:46> reserved valid valid 06 reg<53:48> matrix out in0 of lut3_13 o r clock input of dff10 valid valid reg<55:54> reserved valid valid 07 reg<61:56> matrix out in1 of lut3_13 o r data input of dff10 valid valid reg<63:62> reserved valid valid 08 reg<69:64> matrix out in2 of lut3_13 or rstb (setb) of dff10 valid valid reg<71:70> reserved valid valid 09 reg<77:72> matrix out in0 of lut3_14 o r clock input of dff11 valid valid reg<79:78> reserved valid valid 0a reg<85:80> matrix out in1 of lut3_14 o r data input of dff11 valid valid reg<87:86> reserved valid valid 0b reg<93:88> matrix out in2 of lut3_14 or rstb (setb) of dff11 valid valid reg<95:94> reserved valid valid 0c reg<101:96> matrix out in0 of lut3_15 o r clock input of dff12 valid valid reg<103:102> reserved valid valid 0d reg<109:104> matrix out in1 of lut3_15 o r data input of dff12 valid valid reg<111:110> reserved valid valid
SLG46536_ds_105 page 129 of 164 SLG46536 0e reg<117:112> matrix out in2 of lut3_15 or rstb (setb) of dff12 valid valid reg<119:118> reserved valid valid 0f reg<125:120> matrix out in0 of lut3_16 o r clock input of dff13 valid valid reg<127:126> reserved valid valid 10 reg<133:128> matrix out in1 of lut3_16 or data input of dff13 valid valid reg<135:134> reserved valid valid 11 reg<141:136> matrix out in2 of lut3_16 or rstb (setb) of dff13 valid valid reg<143:142> reserved valid valid 12 reg<149:144> matrix out in0 of lut3_17 o r clock input of dff14 valid valid reg<151:150> reserved valid valid 13 reg<157:152> matrix out in1 of lut3_17 or data input of dff14 valid valid reg<159:158> reserved valid valid 14 reg<165:160> matrix out in2 of lut3_17 or rstb (setb) of dff14 valid valid reg<167:166> reserved valid valid 15 reg<173:168> matrix out in0 of lut4_2 valid valid reg<175:174> reserved valid valid 16 reg<181:176> matrix out in1 of lut4_2 valid valid reg<183:182> reserved valid valid 17 reg<189:184> matrix ou in2 of lut4_2 valid valid reg<191:190> reserved valid valid 18 reg<197:192> matrix out in3 of lut4_2 valid valid reg<199:198> reserved valid valid 19 reg<205:200> reserved valid valid reg<207:206> reserved valid valid 1a reg<213:208> reserved valid valid reg<215:214> reserved valid valid 1b reg<221:216> matrix out pin3 digital output source valid valid reg<223:222> reserved valid valid 1c reg<229:224> reserved valid valid reg<231:230> reserved valid valid 1d reg<237:232> reserved valid valid reg<239:238> reserved valid valid 1e reg<245:240> matrix out pin4 digital output source valid valid reg<247:246> reserved valid valid 1f reg<253:248> matrix out pin5 digital output source valid valid reg<255:254> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 130 of 164 SLG46536 20 reg<261:256> matrix out pin5 output enable valid valid reg<263:262> reserved valid valid 21 reg<269:264> matrix out pin6 digital output source (scl with vi/input & nmos open-drain) valid valid reg<271:270> reserved valid valid 22 reg<277:272> matrix out pin7 digital output source (sda with vi/input & nmos open-drain) valid valid reg<279:278> reserved valid valid 23 reg<285:280> matrix out pin8 digital output source valid valid reg<287:286> reserved valid valid 24 reg<293:288> matrix out pin8 output enable valid valid reg<295:294> reserved valid valid 25 reg<301:296> matrix out pin10 digital output source valid valid reg<303:302> reserved valid valid 26 reg<309:304> reserved valid valid reg<311:310> reserved valid valid 27 reg<317:312> reserved valid valid reg<319:318> reserved valid valid 28 reg<325:320> matrix out pin11 digital output source valid valid reg<327:326> reserved valid valid 29 reg<333:328> matrix out pin11 output enable valid valid reg<335:334> reserved valid valid 2a reg<341:336> reserved valid valid reg<343:342> reserved valid valid 2b reg<349:344> matrix out pin12 digital output source valid valid reg<351:350> reserved valid valid 2c reg<357:352> matrix out pin12 output enable valid valid reg<359:358> reserved valid valid 2d reg<365:360> matrix out pin13 digital output source valid valid reg<367:366> reserved valid valid 2e reg<373:368> reserved valid valid reg<375:374> reserved valid valid 2f reg<381:376> reserved valid valid reg<383:382> reserved valid valid 30 reg<389:384> reserved valid valid reg<391:390> reserved valid valid 31 reg<397:392> reserved valid valid reg<399:398> reserved valid valid 32 reg<405:400> matrix out pin14 digital output source valid valid reg<407:406> reserved valid valid 33 reg<413:408> matrix out acmp0 pdb (power down) valid valid reg<415:414> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 131 of 164 SLG46536 34 reg<421:416> matrix out acmp1 pdb (power down) valid valid reg<423:422> reserved valid valid 35 reg<429:424> matrix out acmp2 pdb (power down) valid valid reg<431:430> reserved valid valid 36 reg<437:432> reserved valid valid reg<439:438> reserved valid valid 37 reg<445:440> matrix out input of filter_0 with fixed time edge detector valid valid reg<447:446> reserved valid valid 38 reg<453:448> matrix out input of filter_1 with fixed time edge detector valid valid reg<455:454> reserved valid valid 39 reg<461:456> matrix out input of programmable delay & edge detector valid valid reg<463:462> reserved valid valid 3a reg<469:464> matrix out osc 25khz/2mhz pd (power down) valid valid reg<471:470> reserved valid valid 3b reg<477:472> matrix out osc 25 mhz pd (power down) valid valid reg<479:478> reserved valid valid 3c reg<485:480> matrix out in0 of lut2_0 or clock input of dff0 valid valid reg<487:486> reserved valid valid 3d reg<493:488> matrix out in1 of lut2_0 or data input of dff0 valid v alid reg<495:494> reserved valid valid 3e reg<501:496> matrix out in0 of lut2_1 or clock input of dff1 vali dvalid reg<503:502> reserved valid valid 3f reg<509:504> matrix out in1 of lut2_1 or data input of dff1 valid v alid reg<511:510> reserved valid valid 40 reg<517:512> matrix out in0 of lut2_2 or clock input of dff2 valid valid reg<519:518> reserved valid valid 41 reg<525:520> matrix out in1 of lut2_2 or data input of dff2 valid v alid reg<527:526> reserved valid valid 42 reg<533:528> matrix out in0 of lut2_3 or clock input of pgen valid valid reg<535:534> reserved valid valid 43 reg<541:536> matrix out in1 of lut2_3 or rstb of pgen valid valid reg<543:542> reserved valid valid 44 reg<549:544> matrix out in0 of lut3_0 or clock input of dff3 vali dvalid reg<551:550> reserved valid valid 45 reg<557:552> matrix out in1 of lut3_0 or data input of dff3 valid v alid reg<559:558> reserved valid valid 46 reg<565:560> matrix out in2 of lut3_0 or rstb (setb) of dff3 valid valid reg<567:566> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 132 of 164 SLG46536 47 reg<573:568> matrix out in0 of lut3_1 or clock input of dff4 valid valid reg<575:574> reserved valid valid 48 reg<581:576> matrix out in1 of lut3_1 or data input of dff4 valid v alid reg<583:582> reserved valid valid 49 reg<589:584> matrix out in2 of lut3_1 or rstb (setb) of dff4 valid valid reg<591:590> reserved valid valid 4a reg<597:592> matrix out in0 of lut3_2 or clock input of dff5 valid valid reg<599:598> reserved valid valid 4b reg<605:600> matrix out in1 of lut3_2 or data input of dff5 valid v alid reg<607:606> reserved valid valid 4c reg<613:608> matrix out in2 of lut3_2 or rstb (setb) of dff5 valid valid reg<615:614> reserved valid valid 4d reg<621:616> matrix out in0 of lut3_3 or clock input of dff6 valid valid reg<623:622> reserved valid valid 4e reg<629:624> matrix out in1 of lut3_3 or data input of dff6 valid v alid reg<631:630> reserved valid valid 4f reg<637:632> matrix out in2 of lut3_3 or rstb (setb) of dff6 valid valid reg<639:638> reserved valid valid 50 reg<645:640> matrix out in0 of lut3_4 or clock input of dff7 vali dvalid reg<647:646> reserved valid valid 51 reg<653:648> matrix out in1 of lut3_4 or data input of dff7 valid v alid reg<655:654> reserved valid valid 52 reg<661:656> matrix out in2 of lut3_4 or rstb (setb) of dff7 valid valid reg<663:662> reserved valid valid 53 reg<669:664> matrix out in0 of lut3_5 or d elay2 input (or counter2 rst input) valid valid reg<671:670> reserved valid valid 54 reg<677:672> matrix out in1 of lut3_5 or external clock input of delay2 (or counter2) valid valid reg<679:678> reserved valid valid 55 reg<685:680> matrix out in2 of lut3_5 valid valid reg<687:686> reserved valid valid 56 reg<693:688> matrix out in0 of lut3_6 or d elay3 input (or counter3 rst input) valid valid reg<695:694> reserved valid valid 57 reg<701:696> matrix out in1 of lut3_6 or external clock input of delay3 (or counter3) valid valid reg<703:702> reserved valid valid 58 reg<709:704> matrix out in2 of lut3_6 valid valid reg<711:710> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 133 of 164 SLG46536 59 reg<717:712> matrix out in0 of lut3_7 or d elay4 input (or counter4 rst input) valid valid reg<719:718> reserved valid valid 5a reg<725:720> matrix out in1 of lut3_7 or external clock input of delay4 (or counter4) valid valid reg<727:726> reserved valid valid 5b reg<733:728> matrix out in2 of lut3_7 valid valid reg<735:734> reserved valid valid 5c reg<741:736> matrix out in0 of lut3_8 or d elay5 input (or counter5 rst input) valid valid reg<743:742> reserved valid valid 5d reg<749:744> matrix out in1 of lut3_8 or external clock input of delay5 (or counter5) valid valid reg<751:750> reserved valid valid 5e reg<757:752> matrix out in2 of lut3_8 valid valid reg<759:758> reserved valid valid 5f reg<765:760> matrix out in0 of lut3_9 or d elay6 input (or counter6 rst input) valid valid reg<767:766> reserved valid valid 60 reg<773:768> matrix out in1 of lut3_9 or external clock input of delay6 (or counter6) valid valid reg<775:774> reserved valid valid 61 reg<781:776> matrix out in2 of lut3_9 valid valid reg<783:782> reserved valid valid 62 reg<789:784> matrix out in0 of lut3_10 or input of pipe delay vali dvalid reg<791:790> reserved valid valid 63 reg<797:792> matrix out in1 of lut3_10 or rstb of pipe de- lay valid valid reg<799:798> reserved valid valid 64 reg<805:800> matrix out in2 of lut3_10 or clock of pipe delay vali dvalid reg<807:806> reserved valid valid 65 reg<813:808> matrix out in0 of lut4_0 or d elay0 input (or counter0 rst/set input) valid valid reg<815:814> reserved valid valid 66 reg<821:816> matrix out in1 of lut4_0 or external clock input of delay0 (or counter0) valid valid reg<823:822> reserved valid valid 67 reg<829:824> matrix out in2 of lut4_0 or up input of fsm0 valid val id reg<831:830> reserved valid valid 68 reg<837:832> matrix out in3 of lut4_0 or keep input of fsm0 valid v alid reg<839:838> reserved valid valid 69 reg<845:840> matrix out in0 of lut4_1 or d elay1 input (or counter1 rst/set input) valid valid reg<847:846> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 134 of 164 SLG46536 6a reg<853:848> matrix out in1 of lut4_1 or external clock input of delay1 (or counter1) valid valid reg<855:854> reserved valid valid 6b reg<861:856> matrix out in2 of lut4_1 or up input of fsm1 valid val id reg<863:862> reserved valid valid 6c reg<869:864> matrix out in3 of lut4_1 or keep input of fsm1 valid v alid reg<871:870> reserved valid valid 6d reg<877:872> matrix out pd of crystal oscillator by reg<1268> val id valid reg<879:878> reserved valid valid reserved 6e reg<887:880> reserved valid valid 6f reg<895:888> reserved valid valid 70 reg<903:896> reserved valid valid 71 reg<911:904> reserved valid valid 72 reg<919:912> reserved valid valid 73 reg<927:920> reserved valid valid 74 reg<935:928> reserved valid valid 75 reg<943:936> reserved valid valid 76 reg<951:944> reserved valid valid 77 reg<959:952> reserved valid valid 78 reg<967:960> reserved valid valid 79 reg<975:968> reserved valid valid 7a reg<983:976> reserved valid valid 7b reg<991:984> reserved valid valid 7c reg<999:992> reserved valid valid 7d reg<1007:1000> reserved valid valid 7e reg<1015:1008> reserved valid valid 7f reg<1023:1016> reserved valid valid pin 2 80 reg<1024> reserved valid valid reg<1025> reserved valid valid reg<1027:1026> reserved valid valid reg<1029:1028> pin2 pull down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1031:1030> pin2 mode control 00: digital input wit hout schmitt trig- ger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved valid valid reserved address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 135 of 164 SLG46536 81 reg<1032> reserved reg<1033> reserved reg<1035:1034> reserved reg<1037:1036> reserved reg<1039:1038> reserved pin 3 82 reg<:1041> pin3 driver strength selection 0: 1x 1: 2x valid valid reg<:1042> pin3 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1044:1043> pin3 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1047:1045> pin3 mode control 000: digital input without schmitt trig- ger 001: digital input wit h schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain nmos valid valid reserved 83 reg<1048> reserved reg<1049> reserved reg<1051:1050> reserved reg<1053:1052> reserved reg<1055:1054> reserved pin 4 84 reg<:1056> reserved valid valid reg<:1057> pin4 driver strength selection 0: 1x 1: 2x valid valid reg<:1058> pin4 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1060:1059> pin4 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1063:1061> pin4 mode control 000: digital input without schmitt trig- ger 001: digital input wit h schmitt trigger 010: low voltage digital input 011: analog input/output 100: push pull 101: open drain nmos 110: open drain pmos 111: analog input & open drain valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 136 of 164 SLG46536 pin 5 85 reg<1064> reserved valid valid reg<1065> pin5 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1067:1066> pin5 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1069:1068> pin5 mode control (sig_pin5_oe=0) 00: digital input wit hout schmitt trig- ger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1071:1070> pin5 mode control (sig_pin5_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid pin 6 86 reg<:1072> reserved valid valid reg<:1073> io6 driver strength selection 0: 1x 1: 2x valid valid reg<:1074> select scl & v irtual input 0 or pin6 0: scl & virtual input 0 1: pin6 valid valid reg<1076:1075> pin6 (or scl) pull down resistor value se- lection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1079:1077> pin6 (or scl) mode control (input mode is selected by reg at scl) 000: digital input without schmitt trig- ger 001: digital input wit h schmitt trigger 010: low voltage digital input 011: reserved 100: open drain nmos 101: open drain nmos 110: open drain nmos 111: reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 137 of 164 SLG46536 pin 7 87 reg<:1080> reserved valid valid reg<:1081> pin7 (or sda) dr iver strength selection 0: 1x (i 2 c up to 400 khz) 1: 2x (i 2 c up to 1 mhz) valid valid reg<:1082> select sda & v irtual input 1 or pin7 0: sda & virtual input 1 1: pin7 valid valid reg<1084:1083> pin7 (or sda) pull down resistor value se- lection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1087:1085> pin9 (or sda) mode control (input mode is selected by reg. but, output mode is fixed as od at sda) 000: digital input without schmitt trig- ger 001: digital input wit h schmitt trigger 010: low voltage digital input 0 11 : r e s e r v e d 100: open drain nmos 101: open drain nmos 110: open drain nmos 111: reserved valid valid pin 8 88 reg<1088> pin8 super drive (4x, nmos open drain) selection 0: super drive off 1: super drive on (if sig_pin8_oe='1' & pin8 mode control = '1x') valid valid reg<1089> pin8 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1091:1090> pin8 pull up/down resistor value selection 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1093:1092> pin8 mode control (sig_pin8_oe=0) 00: digital input wit hout schmitt trig- ger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1095:1094> pin8 mode control (sig_pin8_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid reserved 8a reg<1104> reserved reg<1105> reserved reg<1107:1106> reserved reg<1109:1108> reserved reg<1111:1110> reserved address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 138 of 164 SLG46536 pin 11 8b reg<1112> reserved valid valid reg<1113> pin11 pull up/d own resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1115:1114> pin11 pull up/down re sistor value selec- tion 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1117:1116> pin11 mode control (sig_pin11_oe=0) 00: digital input wit hout schmitt trig- ger 01: digital input with schmitt trigger 10: low voltage digital input 11: analog input/output valid valid reg<1119:1118> pin11 mode control (sig_pin11_oe=1) 00: push pull 1x 01: push pull 2x 10: reserved 11: reserved valid valid reserved 8c reg<1120> reserved reg<1121> reserved reg<1122> reserved reg<1124:1123> reserved reg<1127:1125> reserved pin 12 8d reg<1128> reserved valid valid reg<1129> pin12 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1131:1130> pin12 pull up/down resistor value selec- tion 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1133:1132> pin12 mode control (sig_pin12_oe=0) 00: digital input wit hout schmitt trig- ger 01: digital input with schmitt trigger 10: low voltage digital input 11: reserved valid valid reg<1135:1134> pin12 mode control (sig_pin12_oe=1) 00: push pull 1x 01: push pull 2x 10: open drain nmos 1x 11: open drain nmos 2x valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 139 of 164 SLG46536 pin 13 8e reg<1136> x1 & x2 for crystal osc enable 0: disable 1: enable valid valid reg<1137> pin13 driver strength selection 0: 1x 1: 2x valid valid reg<1138> pin13 pull up/down resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1140:1139> pin13 pull up/down resistor value selec- tion 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1143:1141> pin13 mode control 000: digital input without schmitt trig- ger 001: digital input wit h schmitt trigger 010: low voltage digital input 011: sel for xosc (x1) 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain nmos valid valid reserved 8f reg<1144> reserved reg<1145> reserved reg<1147:1146> reserved reg<1149:1148> reserved reg<1151:1150> reserved reserved 90 reg<1152> reserved reg<1153> reserved reg<1155:1154> reserved reg<1157:1156> reserved reg<1159:1158> reserved address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 140 of 164 SLG46536 pin 14 91 reg<:1160> reserved valid valid reg<:1161> pin14 driver strength selection 0: 1x 1: 2x valid valid reg<:1162> pin14 pull up/d own resistor selection 0: pull down resistor 1: pull up resistor valid valid reg<1164:1163> pin14 pull up/down resistor value selec- tion 00: floating 01: 10 k 10: 100 k 11: 1 m valid valid reg<1167:1165> pin14 mode control 000: digital input without schmitt trig- ger 001: digital input wit h schmitt trigger 010: low voltage digital input 011: reserved 100: push pull 101: open drain nmos 110: open drain pmos 111: open drain nmos valid valid acmp1 92 reg<1168> acmp1 positive input source select 0: io8 1: acmp0 in+ source valid valid reg<1169> acmp1 analog buffer enable (max. bw 1mhz) 0: disable analog buffer 1: enable analog buffer valid valid reg<1171:1170> acmp1 hysteresis enable 00: 0 mv 01: 25 mv 10: 50 mv 11: 200 mv valid valid acmp0 92 reg<1172> acmp0 positive i nput source select 0: io4 1: vdd valid valid reg<1173> acmp0 analog buffer enable (max. bw 1mhz) 0: disable analog buffer 1: enable analog buffer valid valid reg<1175:1174> acmp0 hysteresis enable 00: 0 mv 01: 25 mv 10: 50 mv 11: 200 mv valid valid reserved 93 reg<1177:1176> reserved reg<1179:1178> reserved acmp2 93 reg<1180> reserved reg<1182:1181> acmp2 hysteresis enable 00: 0 mv 01: 25 mv 10: 50 mv 11: 200 mv valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 141 of 164 SLG46536 acmp1 100 ua current source enable 93 reg<1183> acmp1 100ua current source enable 0: disable 1: enable valid valid lut3_x function select 94 reg<1184> lut3_3 or dff6 with rstb/setb select 0: lut3_3 1: dff6 with rstb/setb valid valid reg<1185> lut3_2 or dff5 with rstb/setb select 0: lut3_2 1: dff5 with rstb/setb valid valid reg<1186> lut3_1 or dff4 with rstb/setb select 0: lut3_1 1: dff4 with rstb/setb valid valid reg<1187> lut3_0 or dff3 with rstb/setb select 0: lut3_0 1: dff3 with rstb/setb valid valid lut2_x function select 94 reg<1188> lut2_3 or pgen select 0: lut2_3 1: pgen valid valid reg<1189> lut2_2 or dff2 select 0: lut2_2 1: dff2 valid valid reg<1190> lut2_1 or dff1 select 0: lut2_1 1: dff1 valid valid reg<1191> lut2_0 or dff0 select 0: lut2_0 1: dff0 valid valid lut4_x function select 95 reg<1192> lut4_1 or dly/cnt1(16bits) select 0: lut4_1 1: dly/cnt1(16bits) valid valid reg<1193> lut4_0 or dly/cnt0(16bits) select 0: lut4_0 1: dly/cnt0(16bits) valid valid lut3_x function select 95 reg<1194> lut3_9 or dly/cnt6(8bits) select 0: lut3_9 1: dly/cnt6(8bits) valid valid reg<1195> lut3_8 or dly/cnt5(8bits) select 0: lut3_8 1: dly/cnt5(8bits) valid valid reg<1196> lut3_7 or dly/cnt4(8bits) select 0: lut3_7 1: dly/cnt4(8bits) valid valid reg<1197> lut3_6 or dly/cnt3(8bits) select 0: lut3_6 1: dly/cnt3(8bits) valid valid reg<1198> lut3_5 or dly/cnt2(8bits) select 0: lut3_5 1: dly/cnt2(8bits) valid valid reg<1199> lut3_4 or dff7 with rstb/setb select 0: lut3_4 1: dff7 with rstb/setb valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 142 of 164 SLG46536 lut2_1 / dff1 96 reg<1200> lut2_1 <0> valid valid reg<1201> lut2_1 <1> / dff1 initial polarity select 0: low 1: high valid valid reg<1202> lut2_1 <2> / dff1 output select 0: q output 1: qb output valid valid reg<1203> lut2_1 <3> / dff1 or latch select 0: dff function 1: latch function valid valid lut2_0 / dff0 96 reg<1204> lut2_0 <0> valid valid reg<1205> lut2_0 <1> / dff0 initial polarity select 0: low 1: high valid valid reg<1206> lut2_0 <2> / dff0 output select 0: q output 1: qb output valid valid reg<1207> lut2_0 <3> / dff0 or latch select 0: dff function 1: latch function valid valid lut2_3 / pgen 97 reg<1211:1208> lut2_3<3:0> or pgen 4bit counter da- ta<3:0> valid valid lut2_2 / dff2 97 reg<1212> lut2_2 <0> valid valid reg<1213> lut2_2 <1> / dff2 initial polarity select 0: low 1: high valid valid reg<1214> lut2_2 <2> / dff2 output select 0: q output 1: qb output valid valid reg<1215> lut2_2 <3> / dff2 or latch select 0: dff function 1: latch function valid valid lut3_0 / dff3 98 reg<1219:1216> lut3_0 <3:0> valid valid reg<1220> lut3_0 <4> / dff3 initial polarity select 0: low 1: high valid valid reg<1221> lut3_0 <5> / dff3 rstb or setb select 0: rstb from matrix output 1: setb from matrix output valid valid reg<1222> lut3_0 <6> / dff3 output select 0: q output 1: qb output valid valid reg<1223> lut3_0 <7> / dff3 or latch select 0: dff function 1: latch function valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 143 of 164 SLG46536 lut3_1 / dff4 99 reg<1227:1224> lut3_1 <3:0> valid valid reg<1228> lut3_1 <4> / dff4 initial polarity select 0: low 1: high valid valid reg<1229> lut3_1 <5> / dff4 rstb or setb select 0: rstb from matrix output 1: setb from matrix output valid valid reg<1230> lut3_1 <6> / dff4 output select 0: q output 1: qb output valid valid reg<1231> lut3_1 <7> / dff4 or latch select 0: dff function 1: latch function valid valid lut3_2 / dff5 9a reg<1235:1232> lut3_2 <3:0> valid valid reg<1236> lut3_2 <4> / dff5 initial polarity select 0: low 1: high valid valid reg<1237> lut3_2 <5> / dff5 rstb or setb select 0: rstb from matrix output 1: setb from matrix output valid valid reg<1238> lut3_2 <6> / dff5 output select 0: q output 1: qb output valid valid reg<1239> lut3_2 <7> / dff5 or latch select 0: dff function 1: latch function valid valid lut3_3 / dff6 9b reg<1243:1240> lut3_3 <3:0> valid valid reg<1244> lut3_3 <4> / dff6 initial polarity select 0: low 1: high valid valid reg<1245> lut3_3 <5> / dff6 rstb or setb select 0: rstb from matrix output 1: setb from matrix output valid valid reg<1246> lut3_3 <6> / dff6 output select 0: q output 1: qb output valid valid reg<1247> lut3_3 <7> / dff6 or latch select 0: dff function 1: latch function valid valid lut3_4 / dff7 9c reg<1251:1248> lut3_4 <3:0> valid valid reg<1252> lut3_4 <4> / dff7 initial polarity select 0: low 1: high valid valid reg<1253> lut3_4 <5> / dff7 rstb or setb select 0: rstb from matrix output 1: setb from matrix output valid valid reg<1254> lut3_4 <6> / dff7 output select 0: q output 1: qb output valid valid reg<1255> lut3_4 <7> / dff7 or latch select 0: dff function 1: latch function valid valid lut3_10 / pipe delay 9d reg<1259:1256> lut3_10 <3:0> / pipe delay out0 select valid valid reg<1263:1260> lut3_10 <7:4> / pipe delay out1 select valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 144 of 164 SLG46536 9e reg<1265:1264> select the edge mode of programmable de- lay & edge detector 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay valid valid reg<1267:1266> delay value select for programmable delay & edge detector (vdd = 3.3 v, typical) 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns valid valid reg<1269:1268> crystal oscillator power down enable 00: no matrix pd 01: matrix pd for crystal oscillator 10: reserved 11: reserved valid valid reg<1270> lut3_10 or pipe delay select 0: lut3_10 1: pipe delay valid valid reg<1271> pipe delay out1 polarity select 0: non-inverted 1: inverted valid valid dly/cnt2 9f reg<1273:1272> dly2 mode select or asynchronous cnt2 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on eith er falling or ris- ing edges / high level reset valid valid reg<1276:1274> dly/cnt2 clock source select 000: interna l osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter1 overflow valid valid reg<1277> dly/cnt2 output selection if dly/cnt2 mode selection is "11" 0: default output 1: edge detector output valid valid reg<1279:1278> dly/cnt2 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 145 of 164 SLG46536 dly/cnt3 a0 reg<1281:1280> dly3 mode select or asynchronous cnt3 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on eith er falling or ris- ing edges / high level reset valid valid reg<1284:1282> dly/cnt3 clock source select 000: interna l osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter2 overflow valid valid reg<1285> dly/cnt3 output selection if dly/cnt3 mode selection is "11" 0: default output 1: edge detector output valid valid reg<1287:1286> dly/cnt3 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid dly/cnt4 a1 reg<1289:1288> dly4 mode select or asynchronous cnt4 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on eith er falling or ris- ing edges / high level reset valid valid reg<1292:1290> dly/cnt4 clock source select 000: interna l osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter3 overflow valid valid reg<1293> dly/cnt4 output selection if dly/cnt4 mode selection is "11" 0: default output 1: edge detector output valid valid reg<1295:1294> dly/cnt4 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 146 of 164 SLG46536 dly/cnt5 a2 reg<1297:1296> dly5 mode select or asynchronous cnt5 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on eith er falling or ris- ing edges / high level reset valid valid reg<1300:1298> dly/cnt5 clock source select 000: interna l osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter4 overflow valid valid reg<1301> dly/cnt5 output selection if dly/cnt5 mode selection is "11" 0: default output 1: edge detector output valid valid reg<1303:1302> dly/cnt5 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid dly/cnt6 a3 reg<1305:1304> dly6 mode select or asynchronous cnt6 reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on eith er falling or ris- ing edges / high level reset valid valid reg<1308:1306> dly/cnt6 clock source select 000: interna l osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25mhz osc clock 110: external clock 111: counter5 overflow valid valid reg<1309> dly/cnt6 output selection if dly/cnt6 mode selection is "11" 0: default output 1: edge detector output valid valid reg<1311:1310> dly/cnt6 mode selection 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 147 of 164 SLG46536 dly/cnt0 a4 reg<1313:1312> dly0 mode select or asynchronous cnt0 reset (16bits) 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on eith er falling or ris- ing edges / high level reset or set valid valid reg<1316:1314> dly/cnt0 clo ck source select (16bits) 000: interna l osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter6 overflow valid valid reg<1317> cnt0/fsm0's q are set to data or reset to 0s selection (16bits) 0: reset to 0s 1: set to data (r eg<1583:1576, 1591:1584>) valid valid reg<1319:1318> dly/cnt0 mode selection (16bits) 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid dly/cnt1 a5 reg<1321:1320> dly1 mode select or asynchronous cnt1 reset (16bits) 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on eith er falling or ris- ing edges / high level reset or set valid valid reg<1324:1322> dly/cnt1 clo ck source select (16bits) 000: interna l osc clock 001: osc/4 010: osc/12 011: osc/24 100: osc/64 101: 25 mhz osc clock 110: external clock 111: counter0 overflow valid valid reg<1325> cnt1/fsm1's q are set to data or reset to 0s selection (16bits) 0: reset to 0 s 1: set to data (r eg<1599:1592, 1607:1600>) valid valid reg<1327:1326> dly/cnt1 mode selection (16bits) 00: delay mode 01: one shot 10: freq. detect 11: counter mode valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 148 of 164 SLG46536 dly/cntx one-shot / freq. detect output polarity a6 reg<1328> reserved valid valid reg<1329> select the polarity of dly/cnt6's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1330> select the polarity of dly/cnt5's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1331> select the polarity of dly/cnt4's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1332> select the polarity of dly/cnt3's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1333> select the polarity of dly/cnt2's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1334> select the polarity of dly/cnt1's one shot / freq. detect output 0: default output 1: inverted output valid valid reg<1335> select the polarity of dly/cnt0's one shot / freq. detect output 0: default output 1: inverted output valid valid oscillator a7 reg<1337:1336> osc clock pre-divider for 25 mhz 00: div1 01: div2 10: div4 11: div8 valid valid reg<1338> osc fast start-up enable for 25khz/2mhz 0: disable 1: enable valid valid reg<1340:1339> osc clock pre-divider for 25khz/2mhz 00: div1 01: div2 10: div4 11: div8 valid valid reg<1341> force 25 mhz oscillator on 0: auto power on (if any cnt/dly use 25 mhz source) 1: force power on valid valid reg<1342> oscillator (25 khz: ring osc, 2 m: rc-osc) select 0: 25 khz ring osc 1: 2 mhz rc-osc valid valid reg<1343> force 25 khz /2 mhz oscillator on 0: auto power on (if any cnt/dly use 25 k/2 mhz source) 1: force power on valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 149 of 164 SLG46536 a8 reg<1346:1344> internal osc 25 khz/2 mhz frequency di- vider control for matrix input <28> 000: osc/1 001: osc/2 010: osc/3 011: osc/4 100: osc/8 101: osc/12 110: osc/24 111: osc/64 valid valid reg<1349:1347> internal osc 25 khz/2 mhz frequency di- vider control for matrix input <27> 000: osc/1 001: osc/2 010: osc/3 011: osc/4 100: osc/8 101: osc/12 110: osc/24 111: osc/64 valid valid reg<1350> osc clock 25 khz/2 mhz to matrix input <28> enable 0: disable 1: enable valid valid reg<1351> osc clock 25 khz/2 mhz to matrix input <27> enable 0: disable 1: enable valid valid a9 reg<1354:1352> reserved valid valid reg<1355> reserved reserved valid valid reg<1356> osc clock 25 mhz to matrix input <29> en- able 0: disable 1: enable valid valid reg<1357> external clock source s elect instead of 25 mhz 0: internal oscillator 1: external clock from pin13 valid valid reg<1358> external clock source s elect instead of 25 khz/2 mhz 0: internal oscillator 1: external clock from pin14 valid valid reg<1359> dly/cnt1 stop & resta rting enable in cnt mode when new data is loaded 0: disable 1: enable valid valid lut3 or dff aa reg<1360> reserved valid valid reg<1361> lut3_17 or dff14 with rstb/setb select 0: lut3_17 1: dff14 with rstb/setb valid valid reg<1362> lut3_16 or dff13 with rstb/setb select 0: lut3_16 1: dff13 with rstb/setb valid valid reg<1363> lut3_15 or dff12 with rstb/setb select 0: lut3_15 1: dff12 with rstb/setb valid valid reg<1364> lut3_14 or dff11 with rstb/setb select 0: lut3_14 1: dff11 with rstb/setb valid valid reg<1365> lut3_13 or dff10 with rstb/setb select 0: lut3_13 1: dff10 with rstb/setb valid valid reg<1366> lut3_12 or dff9 with rstb/setb select 0: lut3_12 1: dff9 with rstb/setb valid valid reg<1367> lut3_11 or dff8 with rstb/setb select 0: lut3_11 1: dff8 with rstb/setb valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 150 of 164 SLG46536 ab reg<1371:1368> lut3_11 <3:0> valid valid reg<1372> lut3_11 <4> / dff8 initial polarity select 0: low 1: high valid valid reg<1373> lut3_11 <5> / dff8 rstb or setb select 0: rstb from matrix output 1: setb from matrix output valid valid reg<1374> lut3_11 <6> / dff8 output select 0: q output 1: qb output valid valid reg<1375> lut3_11 <7> / dff8 or latch select 0: dff function 1: latch function valid valid ac reg<1379:1376> lut3_12 <3:0> valid valid reg<1380> lut3_12 <4> / dff9 initial polarity select 0: low 1: high valid valid reg<1381> lut3_12 <5> / dff9 rstb or setb select 0: rstb from matrix output 1: setb from matrix output valid valid reg<1382> lut3_12 <6> / dff9 output select 0: q output 1: qb output valid valid reg<1383> lut3_12 <7> / dff9 or latch select 0: dff function 1: latch function valid valid ad reg<1387:1384> lut3_13 <3:0> valid valid reg<1388> lut3_13 <4> / dff10 initial polarity select 0: low 1: high valid valid reg<1389> lut3_13 <5> / dff10 rstb or setb se- lect 0: rstb from matrix output 1: setb from matrix output valid valid reg<1390> lut3_13 <6> / dff10 output select 0: q output 1: qb output valid valid reg<1391> lut3_13 <7> / dff10 or latch select 0: dff function 1: latch function valid valid ae reg<1395:1392> lut3_14 <3:0> valid valid reg<1396> lut3_14 <4> / dff11 initial polarity select 0: low 1: high valid valid reg<1397> lut3_14 <5> / dff11 rstb or setb se- lect 0: rstb from matrix output 1: setb from matrix output valid valid reg<1398> lut3_14 <6> / dff11 output select 0: q output 1: qb output valid valid reg<1399> lut3_14 <7> / dff11 or latch select 0: dff function 1: latch function valid valid af reg<1403:1400> lut3_15 <3:0> valid valid reg<1404> lut3_15 <4> / dff12 initial polarity select 0: low 1: high valid valid reg<1405> lut3_15 <5> / dff12 rstb or setb se- lect 0: rstb from matrix output 1: setb from matrix output valid valid reg<1406> lut3_15 <6> / dff12 output select 0: q output 1: qb output valid valid reg<1407> lut3_15 <7> / dff12 or latch select 0: dff function 1: latch function valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 151 of 164 SLG46536 b0 reg<1411:1408> lut3_16 <3:0> valid valid reg<1412> lut3_16 <4> / dff13 initial polarity select 0: low 1: high valid valid reg<1413> lut3_16 <5> / dff13 rstb or setb se- lect 0: rstb from matrix output 1: setb from matrix output valid valid reg<1414> lut3_16 <6> / dff13 output select 0: q output 1: qb output valid valid reg<1415> lut3_16 <7> / dff13 or latch select 0: dff function 1: latch function valid valid b1 reg<1419:1416> lut3_17 <3:0> valid valid reg<1420> lut3_17 <4> / dff14 initial polarity select 0: low 1: high valid valid reg<1421> lut3_17 <5> / dff14 rstb or setb se- lect 0: rstb from matrix output 1: setb from matrix output valid valid reg<1422> lut3_17 <6> / dff14 output select 0: q output 1: qb output valid valid reg<1423> lut3_17 <7> / dff14 or latch select 0: dff function 1: latch function valid valid b2 reg<1431:1424> lut4_2 <15:0> = <1439:1424> valid valid b3 reg<1439:1432> valid valid b4 reg<1442:1440> reserved valid valid reg<1443> reserved valid valid reg<1446:1444> reserved valid valid reg<1447> reserved valid valid b5 reg<1450:1448> reserved valid valid reg<1451> reserved valid valid reg<1454:1452> reserved valid valid reg<1455> reserved valid valid filter / edge detector b6 reg<1457:1456> select the edge mode of edge detector_1 00: rising edge 01: falling edge 10: both edge 11: delay valid valid reg<1458> filter_1/edge detector_1 output polarity se- lect 0: filter_1 output 1: filter_1 output inverted valid valid reg<1459> filter_1or edge detector_1 select (typ. 30 ns @vdd=3.3 v) 0: filter_1 1: edge detector_1 valid valid reg<1461:1460> select the edge mode of edge detector_0 00: rising edge 01: falling edge 10: both edge 11: delay valid valid reg<1462> filter_0/edge detector_0 output polarity se- lect 0: filter_0 output 1: filter_0 output inverted valid valid reg<1463> filter_0 or edge detector_0 select (typ. 47 ns @vdd=3.3 v) 0: filter_0 1: edge detector_0 valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 152 of 164 SLG46536 vref / bandgap b7 reg<1465:1464> reserved valid valid reg<1466> bandgap ok for acmp output delay time select, the start time i s "resetb_core go to high" 0: 500 us 1: 50 us valid valid reg<1467> reserved valid valid reg<1468> reserved valid valid reg<1469> reserved valid valid reg<1470> reserved valid valid reg<1471> two consecutive dffs enable for sm 0: disable 1: enable valid valid b8 reg<1474:1472> power divider (vdd/3, vdd/4) on/off 0xx: power divider off (if there is no use of vdd/3, vdd/4 @ acmp nega- tive in) 100: reservedb x10: reserved xx1:reserved valid valid reg<1475> vdd bypass enable when device power is 1.8 v 0: regulator auto on 1: regulator off (vdd bypass) valid valid reg<1476> force bandgap on 0: auto-mode 1: enable (if chip i s power down, the bandgap will power down even if it is set to 1) valid valid reg<1477> nvm power down 0: none (or programming enable) 1: power down (or programming dis- able) valid valid reg<1478> reserved valid valid reg<1479> gpio quick charge enable 0: disable 1: enable valid valid b9 reg<1482:1480> reserved valid valid reg<1483> reserved valid valid reg<1486:1484> reserved valid valid reg<1487> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 153 of 164 SLG46536 ba reg<1488> reserved valid valid reg<1489> wake time selection in wake sleep mode 0: short wake time 1: normal wake time valid valid reg<1490> acmp0 wake & sleep function enable 0: disable 1: enable valid valid reg<1491> acmp1 wake & sleep function enable 0: disable 1: enable valid valid reg<1492> acmp2 wake & sleep function enable 0: disable 1: enable valid valid reg<1493> reserved valid valid reg<1494> wake sleep output state when ws oscilla- tor is off or dly/cnt0 high level set/reset at dly/cnt0 mode se lection is "11" 0: low 1: high valid valid reg<1495> wake sleep ratio control mode selection if dly/cnt0 mode selection is "11" 0: default mode 1: wake sleep ratio control mode valid valid bb reg<1503:1496> reserved valid valid bc reg<1511:1504> reserved valid valid bd reg<1519:1512> reserved valid valid be reg<1527:1520> reserved valid valid bf reg<1535:1528> reserved valid valid lut / dly/cnt control data c0 reg<1543:1536> lut3_5 <7:0> or dly/cnt2 control data 1 - 255 (delay time = [counter control data + 1] / freq) valid valid c1 reg<1551:1544> lut3_6 <7:0> or dly/cnt3 control data 1 - 255 (delay time = [counter control data + 1] / freq) valid valid c2 reg<1559:1552> lut3_7 <7:0> or dly/cnt4 control data 1 - 255 (delay time = [counter control data + 1] / freq) valid valid c3 reg<1567:1560> lut3_8 <7:0> or dly/cnt5 control data 1 - 255 (delay time = [counter control data + 1] / freq) valid valid c4 reg<1575:1568> lut3_9 <7:0> or dly/cnt6 control data 1 - 255 (delay time = [counter control data + 1] / freq) valid valid c5 reg<1583:1576> lut4_0 <15:0> or dl y/cnt0 (16bits, <15:0> = <1591:1576>) control data 1 - 16535 (delay time = [counter control data + 2] / freq) valid valid c6 reg<1591:1584> c7 reg<1599:1592> lut4_1 <15:0> or dl y/cnt1 (16bits, <15:0> = <1607:1592>) control data 1 - 65535 (delay time = [counter control data + 2] / freq) valid valid c8 reg<1607:1600> c9 reg<1615:1608> pgen pattern data <15:0> = <1623:1608> valid valid ca reg<1623:1616> address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 154 of 164 SLG46536 acmp0 cb reg<1628:1624> acmp0-in voltage select 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: pin10: ext_vref 11011: pin5: acmp0- 11100: pin10: ext_vref/2 11101: pin5: acmp0-/2 valid valid reg<1630:1629> acmp0 positive input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x valid valid reg<1631> acmp0 low bandwidth (max: 1 mhz) en- a b l e 0: off 1: on valid valid acmp1 cc reg<1636:1632> acmp1-in voltage select 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: pin10: ext_vref 11011: pin10: ext_vref 11100: pin10: ext_vref/2 11101: pin10: ext_vref/2 valid valid reg<1638:1637> acmp1 positive input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x valid valid reg<1639> acmp1 low bandwidth (max: 1 mhz) en- a b l e 0: off 1: on valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 155 of 164 SLG46536 acmp2 cd reg<1644:1640> acmp2-in voltage select 00000: 50 mv 00001: 100 mv 00010: 150 mv 00011: 200 mv 00100: 250 mv 00101: 300 mv 00110: 350 mv 00111: 400 mv 01000: 450 mv 01001: 500 mv 01010: 550 mv 01011: 600 mv 01100: 650 mv 01101: 700 mv 01110: 750 mv 01111: 800 mv 10000: 850 mv 10001: 900 mv 10010: 950 mv 10011: 1 v 10100: 1.05 v 10101: 1.1 v 10110: 1.15 v 10111: 1.2 v 11000: vdd/3 11001: vdd/4 11010: pin10: ext_vref 11011: reserved 11100: pin10: ext_vref/2 11101: reserved valid valid reg<1646:1645> acmp2 positive input divider 00: 1.0x 01: 0.5x 10: 0.33x 11: 0.25x valid valid reg<1647> acmp2 low bandwidth (max: 1 mhz) en- a b l e 0: off 1: on valid valid reserved ce reg<1652:1648> reserved reserved reg<1655> reserved misc. cf reg<1656> reserved valid valid reg<1657> switch from matrix out: osc 25mhz pd to matrix out: osc 25 mhz force on 0: osc pd 1: osc force on (matrix output <59>) valid valid reg<1658> switch from matrix out: osc 25 khz/2 mhz pd to matrix out: osc 25 khz/2 mhz force on 0: osc pd 1: osc force on (matrix output <58>) valid valid reg<1659> reserved valid valid reg<1660> reserved valid valid reg<1661> reserved valid valid reg<1662> i 2 c reset bit with reloading nvm into data register 0: keep existing condition 1 : r e s e t e x e c u t i o n valid valid reg<1663> io latching enable during i 2 c write inter- face 0: disable 1: enable valid valid d0 reg<1671:1664> customer configurable ram8 valid valid d1 reg<1679:1672> customer configurable ram9 valid valid d2 reg<1687:1680> customer configurable ram10 valid valid d3 reg<1695:1688> customer configurable ram11 valid valid d4 reg<1703:1696> customer configurable ram12 valid valid d5 reg<1711:1704> customer configurable ram13 valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 156 of 164 SLG46536 d6 reg<1719:1712> customer configurable ram14 valid valid d7 reg<1727:1720> customer configurable ram15 valid valid d8 reg<1735:1728> customer configurable ram0 invalid invalid d9 reg<1743:1736> customer configurable ram1 invalid invalid da reg<1751:1744> customer configurable ram2 invalid invalid db reg<1759:1752> customer configurable ram3 invalid invalid dc reg<1767:1760> customer configurable ram4 invalid invalid dd reg<1775:1768> customer configurable ram5 invalid invalid de reg<1783:1776> customer configurable ram6 invalid invalid df reg<1791:1784> customer configurable ram7 invalid invalid e0 reg<1799:1792> reserved invalid invalid e1 reg<1807:1800> reserved invalid invalid e2 reg<1815:1808> reserved invalid invalid e3 reg<1823:1816> reserved invalid invalid e4 reg<1831:1824> reserved valid valid e5 reg<1832> i 2 c lock for read bits <1535:0> (bank 0/1/2) 0: disable (programmed data can be read.), 1: enable (programmed data can't be read.) valid invalid reg<1833> reserved valid invalid reg<1835:1834> reserved valid invalid reg<1839:1836> reserved valid invalid e6 reg<1847:1840> 16-bit pattern id byte 0 (from nvm): id[23:16] valid valid e7 reg<1855:1848> reserved valid invalid e8 reg<1863:1856> reserved valid invalid e9 reg<1867:1864> i 2 c control code bit [3:0] value for slave address valid invalid reg<1868> reserved valid valid reg<1869> reserved valid valid reg<1870> i 2 c lock for write all bits (bank 0/1/2/3) 0: writable 1: non-writable valid valid reg<1871> i 2 c lock for write bits <1535:0> (bank 0/1/2) 0: writable 1: non-writable valid invalid ea reg<1879:1872> cnt4 counted value valid invalid eb reg<1887:1880> cnt0 (16bits) = <1895:1880> counted val- ue valid invalid ec reg<1895:1888> valid invalid ed reg<1903:1896> cnt6 counted value valid invalid ee reg<1911:1904> cnt1 (16bits) = <1919:1904> counted val- ue valid invalid ef reg<1919:1912> valid invalid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 157 of 164 SLG46536 matrix input f0 reg<1920> matrix input 0 gnd valid invalid reg<1921> matrix input 1 pin2 digital input valid invalid reg<1922> reserved gnd valid invalid reg<1923> matrix input 3 pin3 digital input valid invalid reg<1924> reserved gnd valid invalid reg<1925> matrix input 5 pin4 digital input valid invalid reg<1926> matrix input 6 pin5 digital input valid invalid reg<1927> matrix input 7 pin8 digital input valid invalid f1 reg<1928> matrix input 8 lut2_ 0 / dff0 output valid invalid reg<1929> matrix input 9 lut2_ 1 / dff1 output valid invalid reg<1930> matrix input 10 lut2_2 / dff2 output valid invalid reg<1931> matrix input 11 lut2_3 / pgen output valid invalid reg<1932> matrix input 12 lut3_0 / dff3 output valid invalid reg<1933> matrix input 13 lut3_1 / dff4 output valid invalid reg<1934> matrix input 14 lut3_2 / dff5 output valid invalid reg<1935> matrix input 15 lut3_3 / dff6 output valid invalid f2 reg<1936> matrix input 16 lut3_4 / dff7 output valid invalid reg<1937> matrix input 17 lut3_5 / cnt_dly2(8bit) output valid inva lid reg<1938> matrix input 18 lut3_6 / cnt_dly3(8bit) output valid inva lid reg<1939> matrix input 19 lut3_7 / cnt_dly4(8bit) output valid inva lid reg<1940> matrix input 20 lut3_8 / cnt_dly5(8bit) output valid inva lid reg<1941> matrix input 21 lut3_9 / cnt_dly6(8bit) output valid inva lid reg<1942> matrix input 22 lut4_0 / cnt_dly0(16bit) output valid in valid reg<1943> matrix input 23 lut4_1 / cnt_dly1(16bit) output valid inv alid f3 reg<1944> matrix input 24 lut3_10 / pipe delay (1st stage) out- put valid invalid reg<1945> matrix input 25 pipe delay output0 valid invalid reg<1946> matrix input 26 pipe delay output1 valid invalid reg<1947> matrix input 27 fixed "l" output because it is osc clock. valid invalid reg<1948> matrix input 28 fixed "l" output because it is osc clock. valid invalid reg<1949> matrix input 29 fixed "l" output because it is osc clock. valid invalid reg<1950> matrix input 30 filter0 / edge detect0 output valid inva lid reg<1951> matrix input 31 filter1 / edge detect1 output valid inva lid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 158 of 164 SLG46536 f4 reg<1952> matrix input 32 vi rtual input <0> valid valid reg<1953> matrix input 33 vi rtual input <1> valid valid reg<1954> matrix input 34 vi rtual input <2> valid valid reg<1955> matrix input 35 vi rtual input <3> valid valid reg<1956> matrix input 36 vi rtual input <4> valid valid reg<1957> matrix input 37 vi rtual input <5> valid valid reg<1958> matrix input 38 vi rtual input <6> valid valid reg<1959> matrix input 39 virt ual input <7> valid valid f5 reg<1960> matrix input 40 lut3_11 / dff8 (set/rst) output valid inv alid reg<1961> matrix input 41 lut3_12 / dff9 (set/rst) output valid inv alid reg<1962> matrix input 42 lut3_13 / dff10 (set/rst) output valid in valid reg<1963> matrix input 43 lut3_14 / dff11 (set/rst) output valid in valid reg<1964> matrix input 44 lut3_15 / dff12 (set/rst) output valid in valid reg<1965> matrix input 45 lut3_16 / dff13 (set/rst) output valid in valid reg<1966> matrix input 46 lut3_17 / dff14 (set/rst) output valid in valid reg<1967> matrix input 47 lut4_2 output valid invalid f6 reg<1968> reserved pin10 digital input valid invalid reg<1969> matrix input 49 gnd valid invalid reg<1970> matrix input 50 pin11 digital input valid invalid reg<1971> reserved gnd valid invalid reg<1972> matrix input 52 pin12 digital input valid invalid reg<1973> matrix input 53 pin13 digital input valid invalid reg<1974> reserved gnd valid invalid reg<1975> reserved gnd valid invalid f7 reg<1976> matrix input 56 pin14 digital input valid invalid reg<1977> matrix input 57 ac mp_0 output valid invalid reg<1978> matrix input 58 ac mp_1 output valid invalid reg<1979> matrix input 59 ac mp_2 output valid invalid reg<1980> matrix input 60 valid invalid reg<1981> matrix input 61 programmable del ay with edge de- tector output valid invalid reg<1982> matrix input 62 resetb_core valid invalid reg<1983> matrix input 63 vdd valid invalid reserved f8 reg<1991:1984> reserved valid invalid f9 reg<1999:1992> reserved valid invalid fa reg<2007:2000> reserved valid invalid fb reg<2015:2008> reserved valid valid fc reg<2023:2016> reserved valid invalid fd reg<2031:2024> reserved valid invalid fe reg<2039:2032> reserved valid valid ff reg<2047:2040> reserved valid valid address signal function register bit definition i 2 c interface byte register bit read write
SLG46536_ds_105 page 159 of 164 SLG46536 21.0 package top marking system definition ppa wwr nn date code + revision part code + assembly site s/n code pin 1 identifier
SLG46536_ds_105 page 160 of 164 SLG46536 22.0 package drawing and dimensions stqfn 14l 2 x 2.2mm 0.4p col package jedec mo-220, variation wece
SLG46536_ds_105 page 161 of 164 SLG46536 23.0 tape and reel specifications 23.1 carrier tape drawing and dimensions package type # of pins nominal package size [mm] max units reel & hub size [mm] leader (min) trailer (min) tape width [mm] part pitch [mm] per reel per box pockets length [mm] pockets length [mm] stqfn 14l 2x2.2 mm 0.4p col 14 2 x 2.2 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4 package type pocket btm length pocket btm width pocket depth index hole pitch pocket pitch index hole diameter index hole to tape edge index hole to pocket center tape width a0 b0 k0 p0 p1 d0 e f w stqfn 14l 2x2.2 mm 0.4p col 2.2 2.35 0.8 4 4 1.5 1.75 3.5 8 refer to eia-481 specification
SLG46536_ds_105 page 162 of 164 SLG46536 24.0 recommended landing pattern 25.0 recommended reflow soldering profile please see ipc/jedec j-std-020: latest revision for reflow prof ile based on package volume of 2.42 mm 3 (nominal). more information can be f ound at www.jedec.org.
SLG46536_ds_105 page 163 of 164 SLG46536 26.0 revision history date version change 10/12/2017 1.05 updated electrical spec fixed typos updated i2c specifications updated subsection i2c serial reset command updated i2c serial command register protection added register read/write protection subsection 5/24/2017 1.04 fixed typos updated reg<1831:1824> updated electrical characteristics 5/5/2017 1.03 fixed quality of cnt timing diagrams updated section programmable delay / edge detector fixed typos updated por section updated absolute maximum conditions corrected table typical delay es timated for each block at t=25 c 12/20/2016 1.02 corrected oscillator electrical spec updated silego w ebsite & support fixed typos corrected figure ws controller added table dly/cntx one-shot / freq. detect output polarity added data to table programma ble delay register settings updated figure deglitch filter / edge detector 11/16/2016 1.01 corrected figure osc1 power on delay corrected table typical counter/delay offset measurements added subsection difference in counter value for counter, delay , one-shot and frequency detect modes 10/21/2016 1.00 production release
SLG46536_ds_105 page 164 of 164 SLG46536 silego website & support silego technology website silego technology provides online support via our website at http://www.silego.com/ .this website is used as a means to make files and information easily available to customers. for more information regarding si lego green products, please vi sit our website. our green product lines feature: greenpak: programmable mixed signal matrix products greenfet1 / greenfet3 / hfet1: mos fet drivers and ultra-small, low rdson load switches greenclk1 / greenclk2 / greenclk 3: crystal replacement technolo gy products are also available for purchase directly from silego a t the silego on line store at http://www.silego.com /buy/ . silego technical support datasheets and errata, application notes and example designs, u ser guides, and hardware support documents and the latest software releases are available at the silego website or can be requested directly at info@silego.com . for specific greenpak design or applications questions and supp ort please send e-mail requests to greenpak@silego.com users of silego products can rec eive assistance through several channels: contact your local sales representative customers can contact their local sales representative or field application engineer (fae) for support. local sales offices ar e also available to help customers. more information regarding your lo cal representative is available at the silego website or send a request to info@silego.com contact silego directly silego can be contacted d irectly via e-mail at info@silego.com or user submission form, l ocated at the f ollowing url: http://support.silego.com/ other information the latest silego technology press releases, listing of seminar s and events, listings of world wide silego technology offices and representatives are all available at http://www.silego.com/ this product has been designed an d qualified for the consumer m arket. applications or uses as critical components in life support devices or systems are n ot authorized. silego technolog y does not assume any liability arising out of such applica- tions or uses of its products. silego technology reserves the r ight to improve product design , functions and reliability without notice .

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